| Message ID | 20170430192244.9623-4-daniel.schwierzeck@gmail.com |
|---|---|
| State | Accepted |
| Commit | ed048e7c763ac9b7043c989ba3081d7a52e4f68e |
| Delegated to: | Daniel Schwierzeck |
| Headers | show |
On 30 April 2017 at 13:22, Daniel Schwierzeck <daniel.schwierzeck@gmail.com> wrote: > From: Paul Burton <paul.burton@imgtec.com> > > Move the MIPS Coherence Manager (CM) Global Configuration Registers > (GCRs) away from the region of the physical address space which the > Boston board's parallel flash is found in, such that we can access all > of flash without clobbering GCRs. > > Signed-off-by: Paul Burton <paul.burton@imgtec.com> > Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> > > --- > > Changes in v2: > - set default value for Boston in arch/mips/Kconfig > > arch/mips/Kconfig | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Simon Glass <sjg@chromium.org>
Am 30.04.2017 um 21:22 schrieb Daniel Schwierzeck: > From: Paul Burton <paul.burton@imgtec.com> > > Move the MIPS Coherence Manager (CM) Global Configuration Registers > (GCRs) away from the region of the physical address space which the > Boston board's parallel flash is found in, such that we can access all > of flash without clobbering GCRs. > > Signed-off-by: Paul Burton <paul.burton@imgtec.com> > Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> > > --- > > Changes in v2: > - set default value for Boston in arch/mips/Kconfig > > arch/mips/Kconfig | 1 + > 1 file changed, 1 insertion(+) > applied to u-boot-mips/master, thanks.
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 77d1ac65d2..07488fe651 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -224,6 +224,7 @@ config ROM_EXCEPTION_VECTORS config MIPS_CM_BASE hex "MIPS CM GCR Base Address" depends on MIPS_CM + default 0x16100000 if TARGET_BOSTON default 0x1fbf8000 help The physical base address at which to map the MIPS Coherence Manager