| Message ID | 20140708014016.GF29202@bill-the-cat |
|---|---|
| State | Awaiting Upstream |
| Delegated to: | Tom Rini |
| Headers | show |
Works for me on the Pepper board. Thanks for the fix! Tested-By: Ash Charles <ashcharles@gmail.com> On Mon, Jul 7, 2014 at 6:40 PM, Tom Rini <trini@ti.com> wrote: > As noted by clang, we have been shifting certain values out of 32bit > range when setting some DDR registers. Upon further inspection these > had been touching reserved fields (and having no impact). These came in > from historical bring-up code and can be discarded. Similarly, we had > been declaring some fields as 0 when they will be initialized that way. > Tested on Beaglebone White. > > Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl> > Cc: Ash Charles <ash@gumstix.com> > Signed-off-by: Tom Rini <trini@ti.com> > --- > arch/arm/include/asm/arch-am33xx/ddr_defs.h | 4 ---- > board/gumstix/pepper/board.c | 30 +++------------------------ > board/ti/am335x/board.c | 30 +++------------------------ > 3 files changed, 6 insertions(+), 58 deletions(-) > > diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h > index 4d89952..97bbfe2 100644 > --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h > +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h > @@ -33,11 +33,7 @@ > #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 > #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a > #define MT47H128M16RT25E_RATIO 0x80 > -#define MT47H128M16RT25E_INVERT_CLKOUT 0x00 > #define MT47H128M16RT25E_RD_DQS 0x12 > -#define MT47H128M16RT25E_WR_DQS 0x00 > -#define MT47H128M16RT25E_PHY_WRLVL 0x00 > -#define MT47H128M16RT25E_PHY_GATELVL 0x00 > #define MT47H128M16RT25E_PHY_WR_DATA 0x40 > #define MT47H128M16RT25E_PHY_FIFO_WE 0x80 > #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B > diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c > index 75aac49..f644f81 100644 > --- a/board/gumstix/pepper/board.c > +++ b/board/gumstix/pepper/board.c > @@ -34,41 +34,17 @@ DECLARE_GLOBAL_DATA_PTR; > > #ifdef CONFIG_SPL_BUILD > static const struct ddr_data ddr2_data = { > - .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | > - (MT47H128M16RT25E_RD_DQS<<20) | > - (MT47H128M16RT25E_RD_DQS<<10) | > - (MT47H128M16RT25E_RD_DQS<<0)), > - .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | > - (MT47H128M16RT25E_WR_DQS<<20) | > - (MT47H128M16RT25E_WR_DQS<<10) | > - (MT47H128M16RT25E_WR_DQS<<0)), > - .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | > - (MT47H128M16RT25E_PHY_WRLVL<<20) | > - (MT47H128M16RT25E_PHY_WRLVL<<10) | > - (MT47H128M16RT25E_PHY_WRLVL<<0)), > - .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | > - (MT47H128M16RT25E_PHY_GATELVL<<20) | > - (MT47H128M16RT25E_PHY_GATELVL<<10) | > - (MT47H128M16RT25E_PHY_GATELVL<<0)), > - .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | > - (MT47H128M16RT25E_PHY_FIFO_WE<<20) | > - (MT47H128M16RT25E_PHY_FIFO_WE<<10) | > - (MT47H128M16RT25E_PHY_FIFO_WE<<0)), > - .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | > - (MT47H128M16RT25E_PHY_WR_DATA<<20) | > - (MT47H128M16RT25E_PHY_WR_DATA<<10) | > - (MT47H128M16RT25E_PHY_WR_DATA<<0)), > + .datardsratio0 = MT47H128M16RT25E_RD_DQS, > + .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, > + .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, > }; > > static const struct cmd_control ddr2_cmd_ctrl_data = { > .cmd0csratio = MT47H128M16RT25E_RATIO, > - .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, > > .cmd1csratio = MT47H128M16RT25E_RATIO, > - .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, > > .cmd2csratio = MT47H128M16RT25E_RATIO, > - .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, > }; > > static const struct emif_regs ddr2_emif_reg_data = { > diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c > index da780ed..d81eec9 100644 > --- a/board/ti/am335x/board.c > +++ b/board/ti/am335x/board.c > @@ -84,41 +84,17 @@ static int read_eeprom(struct am335x_baseboard_id *header) > > #ifndef CONFIG_SKIP_LOWLEVEL_INIT > static const struct ddr_data ddr2_data = { > - .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | > - (MT47H128M16RT25E_RD_DQS<<20) | > - (MT47H128M16RT25E_RD_DQS<<10) | > - (MT47H128M16RT25E_RD_DQS<<0)), > - .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | > - (MT47H128M16RT25E_WR_DQS<<20) | > - (MT47H128M16RT25E_WR_DQS<<10) | > - (MT47H128M16RT25E_WR_DQS<<0)), > - .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | > - (MT47H128M16RT25E_PHY_WRLVL<<20) | > - (MT47H128M16RT25E_PHY_WRLVL<<10) | > - (MT47H128M16RT25E_PHY_WRLVL<<0)), > - .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | > - (MT47H128M16RT25E_PHY_GATELVL<<20) | > - (MT47H128M16RT25E_PHY_GATELVL<<10) | > - (MT47H128M16RT25E_PHY_GATELVL<<0)), > - .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | > - (MT47H128M16RT25E_PHY_FIFO_WE<<20) | > - (MT47H128M16RT25E_PHY_FIFO_WE<<10) | > - (MT47H128M16RT25E_PHY_FIFO_WE<<0)), > - .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | > - (MT47H128M16RT25E_PHY_WR_DATA<<20) | > - (MT47H128M16RT25E_PHY_WR_DATA<<10) | > - (MT47H128M16RT25E_PHY_WR_DATA<<0)), > + .datardsratio0 = MT47H128M16RT25E_RD_DQS, > + .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, > + .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, > }; > > static const struct cmd_control ddr2_cmd_ctrl_data = { > .cmd0csratio = MT47H128M16RT25E_RATIO, > - .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, > > .cmd1csratio = MT47H128M16RT25E_RATIO, > - .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, > > .cmd2csratio = MT47H128M16RT25E_RATIO, > - .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, > }; > > static const struct emif_regs ddr2_emif_reg_data = { > -- > 1.7.9.5
Hello Tom, On 08-07-14 03:40, Tom Rini wrote: > As noted by clang, we have been shifting certain values out of 32bit > range when setting some DDR registers. Upon further inspection these > had been touching reserved fields (and having no impact). These came in > from historical bring-up code and can be discarded. Similarly, we had > been declaring some fields as 0 when they will be initialized that way. > Tested on Beaglebone White. > > Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl> > Cc: Ash Charles <ash@gumstix.com> > Signed-off-by: Tom Rini <trini@ti.com> > --- > arch/arm/include/asm/arch-am33xx/ddr_defs.h | 4 ---- > board/gumstix/pepper/board.c | 30 +++------------------------ > board/ti/am335x/board.c | 30 +++------------------------ > 3 files changed, 6 insertions(+), 58 deletions(-) > Thanks, the warnings are also gone! Regards, Jeroen
On Mon, Jul 07, 2014 at 09:40:16PM -0400, Tom Rini wrote: > As noted by clang, we have been shifting certain values out of 32bit > range when setting some DDR registers. Upon further inspection these > had been touching reserved fields (and having no impact). These came in > from historical bring-up code and can be discarded. Similarly, we had > been declaring some fields as 0 when they will be initialized that way. > Tested on Beaglebone White. > > Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl> > Cc: Ash Charles <ash@gumstix.com> > Signed-off-by: Tom Rini <trini@ti.com> > Tested-By: Ash Charles <ashcharles@gmail.com> Applied to u-boot-ti/master, thanks!
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 4d89952..97bbfe2 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -33,11 +33,7 @@ #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a #define MT47H128M16RT25E_RATIO 0x80 -#define MT47H128M16RT25E_INVERT_CLKOUT 0x00 #define MT47H128M16RT25E_RD_DQS 0x12 -#define MT47H128M16RT25E_WR_DQS 0x00 -#define MT47H128M16RT25E_PHY_WRLVL 0x00 -#define MT47H128M16RT25E_PHY_GATELVL 0x00 #define MT47H128M16RT25E_PHY_WR_DATA 0x40 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c index 75aac49..f644f81 100644 --- a/board/gumstix/pepper/board.c +++ b/board/gumstix/pepper/board.c @@ -34,41 +34,17 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SPL_BUILD static const struct ddr_data ddr2_data = { - .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | - (MT47H128M16RT25E_RD_DQS<<20) | - (MT47H128M16RT25E_RD_DQS<<10) | - (MT47H128M16RT25E_RD_DQS<<0)), - .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | - (MT47H128M16RT25E_WR_DQS<<20) | - (MT47H128M16RT25E_WR_DQS<<10) | - (MT47H128M16RT25E_WR_DQS<<0)), - .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | - (MT47H128M16RT25E_PHY_WRLVL<<20) | - (MT47H128M16RT25E_PHY_WRLVL<<10) | - (MT47H128M16RT25E_PHY_WRLVL<<0)), - .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | - (MT47H128M16RT25E_PHY_GATELVL<<20) | - (MT47H128M16RT25E_PHY_GATELVL<<10) | - (MT47H128M16RT25E_PHY_GATELVL<<0)), - .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | - (MT47H128M16RT25E_PHY_FIFO_WE<<20) | - (MT47H128M16RT25E_PHY_FIFO_WE<<10) | - (MT47H128M16RT25E_PHY_FIFO_WE<<0)), - .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | - (MT47H128M16RT25E_PHY_WR_DATA<<20) | - (MT47H128M16RT25E_PHY_WR_DATA<<10) | - (MT47H128M16RT25E_PHY_WR_DATA<<0)), + .datardsratio0 = MT47H128M16RT25E_RD_DQS, + .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, + .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, }; static const struct cmd_control ddr2_cmd_ctrl_data = { .cmd0csratio = MT47H128M16RT25E_RATIO, - .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd1csratio = MT47H128M16RT25E_RATIO, - .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd2csratio = MT47H128M16RT25E_RATIO, - .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, }; static const struct emif_regs ddr2_emif_reg_data = { diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index da780ed..d81eec9 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -84,41 +84,17 @@ static int read_eeprom(struct am335x_baseboard_id *header) #ifndef CONFIG_SKIP_LOWLEVEL_INIT static const struct ddr_data ddr2_data = { - .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | - (MT47H128M16RT25E_RD_DQS<<20) | - (MT47H128M16RT25E_RD_DQS<<10) | - (MT47H128M16RT25E_RD_DQS<<0)), - .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | - (MT47H128M16RT25E_WR_DQS<<20) | - (MT47H128M16RT25E_WR_DQS<<10) | - (MT47H128M16RT25E_WR_DQS<<0)), - .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | - (MT47H128M16RT25E_PHY_WRLVL<<20) | - (MT47H128M16RT25E_PHY_WRLVL<<10) | - (MT47H128M16RT25E_PHY_WRLVL<<0)), - .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | - (MT47H128M16RT25E_PHY_GATELVL<<20) | - (MT47H128M16RT25E_PHY_GATELVL<<10) | - (MT47H128M16RT25E_PHY_GATELVL<<0)), - .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | - (MT47H128M16RT25E_PHY_FIFO_WE<<20) | - (MT47H128M16RT25E_PHY_FIFO_WE<<10) | - (MT47H128M16RT25E_PHY_FIFO_WE<<0)), - .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | - (MT47H128M16RT25E_PHY_WR_DATA<<20) | - (MT47H128M16RT25E_PHY_WR_DATA<<10) | - (MT47H128M16RT25E_PHY_WR_DATA<<0)), + .datardsratio0 = MT47H128M16RT25E_RD_DQS, + .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, + .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, }; static const struct cmd_control ddr2_cmd_ctrl_data = { .cmd0csratio = MT47H128M16RT25E_RATIO, - .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd1csratio = MT47H128M16RT25E_RATIO, - .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd2csratio = MT47H128M16RT25E_RATIO, - .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, }; static const struct emif_regs ddr2_emif_reg_data = {
As noted by clang, we have been shifting certain values out of 32bit range when setting some DDR registers. Upon further inspection these had been touching reserved fields (and having no impact). These came in from historical bring-up code and can be discarded. Similarly, we had been declaring some fields as 0 when they will be initialized that way. Tested on Beaglebone White. Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: Ash Charles <ash@gumstix.com> Signed-off-by: Tom Rini <trini@ti.com> --- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 4 ---- board/gumstix/pepper/board.c | 30 +++------------------------ board/ti/am335x/board.c | 30 +++------------------------ 3 files changed, 6 insertions(+), 58 deletions(-)