| Message ID | 1709694011-683-1-git-send-email-ganboing@gmail.com |
|---|---|
| State | Accepted |
| Commit | e6b7aeef3df206b9f2a47e715d643b735d18ae73 |
| Delegated to: | Andes |
| Headers | show |
| Series | riscv: dts: jh7110: Enable PLL node in SPL | expand |
On Tue, Mar 05, 2024 at 07:00:11PM -0800, Bo Gan wrote: > Previously PLL node was missing from SPL dts. This caused BUS_ROOT > to stay on OSC clock (24Mhz). As a result, all peripherals have to > run at a much lower frequency, and loading from sdcard/emmc is slow. > Thus, enabling PLL node in dts to fix this. > > Signed-off-by: Bo Gan <ganboing@gmail.com> > --- > arch/riscv/dts/jh7110-u-boot.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> On 06.03.24 11:00, Bo Gan wrote: > > Previously PLL node was missing from SPL dts. This caused BUS_ROOT to stay on > OSC clock (24Mhz). As a result, all peripherals have to run at a much lower > frequency, and loading from sdcard/emmc is slow. > Thus, enabling PLL node in dts to fix this. > > Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Original speed class SD cards fail with this change "unable to change mode". On Tue, Mar 12, 2024 at 4:12 AM Hal Feng <hal.feng@starfivetech.com> wrote: > > > On 06.03.24 11:00, Bo Gan wrote: > > > > Previously PLL node was missing from SPL dts. This caused BUS_ROOT to stay on > > OSC clock (24Mhz). As a result, all peripherals have to run at a much lower > > frequency, and loading from sdcard/emmc is slow. > > Thus, enabling PLL node in dts to fix this. > > > > Signed-off-by: Bo Gan <ganboing@gmail.com> > > Reviewed-by: Hal Feng <hal.feng@starfivetech.com> >
On 4/9/24 6:55 PM, E Shattow wrote: > Original speed class SD cards fail with this change "unable to change mode". > > On Tue, Mar 12, 2024 at 4:12 AM Hal Feng <hal.feng@starfivetech.com> wrote: >> >>> On 06.03.24 11:00, Bo Gan wrote: >>> >>> Previously PLL node was missing from SPL dts. This caused BUS_ROOT to stay on >>> OSC clock (24Mhz). As a result, all peripherals have to run at a much lower >>> frequency, and loading from sdcard/emmc is slow. >>> Thus, enabling PLL node in dts to fix this. >>> >>> Signed-off-by: Bo Gan <ganboing@gmail.com> >> >> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> >> The BUS_ROOT clock will have to be switched to PLL2 anyway in U-Boot proper or in Linux, because it's the parent or grandparent clock for *lots* of devices, including PCIe, i2c, spi, qspi... If there's an issue with this change, then I suspect there's something wrong with the dw_mmc driver. Bo
On Tue, Apr 9, 2024 at 11:44 PM Bo Gan <ganboing@gmail.com> wrote: > > On 4/9/24 6:55 PM, E Shattow wrote: > > Original speed class SD cards fail with this change "unable to change mode". > > > > The BUS_ROOT clock will have to be switched to PLL2 anyway in U-Boot proper or > in Linux, because it's the parent or grandparent clock for *lots* of devices, > including PCIe, i2c, spi, qspi... If there's an issue with this change, then > I suspect there's something wrong with the dw_mmc driver. > > Bo I've bisected and can confirm this change is what breaks original speed SD function on Milk-V Mars CM Lite (DFRobot mini router carrier). Class 10 speed SD media does not seem to be affected. Reverting the change allows the original speed SD media access to function again. SD access is functional in Linux with and without the change. How to troubleshoot this? Thanks, E
On 4/16/24 9:59 PM, E Shattow wrote: > On Tue, Apr 9, 2024 at 11:44 PM Bo Gan <ganboing@gmail.com> wrote: >> >> On 4/9/24 6:55 PM, E Shattow wrote: >>> Original speed class SD cards fail with this change "unable to change mode". >>> >> >> The BUS_ROOT clock will have to be switched to PLL2 anyway in U-Boot proper or >> in Linux, because it's the parent or grandparent clock for *lots* of devices, >> including PCIe, i2c, spi, qspi... If there's an issue with this change, then >> I suspect there's something wrong with the dw_mmc driver. >> >> Bo > > I've bisected and can confirm this change is what breaks original > speed SD function on Milk-V Mars CM Lite (DFRobot mini router > carrier). Class 10 speed SD media does not seem to be affected. > Reverting the change allows the original speed SD media access to > function again. SD access is functional in Linux with and without the > change. > > How to troubleshoot this? > > Thanks, > > E > If without the change (reverted), can you read/write the same SD media in U-boot proper? (U-boot proper will switch BUS_ROOT to PLL2). One potential problem I could think of is perhaps the SPL built is without SPL_PINCTRL_STARFIVE/JH7110 or the u-boot dts is missing the pinctrl that properly sets drive-strength and other properties of the mmc0/1 pins. What dtb are you using? I tested this with visionfive2 and it's working fine. Can you share the tree/config you used to built for Milk-V Mars CM Lite? I don't see the corresponding dts being checked- in to u-boot tree, so it helps if you can share the code. Thanks! Bo
On Fri, Apr 19, 2024 at 5:51 PM Bo Gan <ganboing@gmail.com> wrote: > ...snip... > > If without the change (reverted), can you read/write the same SD media in U-boot > proper? (U-boot proper will switch BUS_ROOT to PLL2). I tested again this change in commit e6b7aeef, before this change in parent commit e6b7aeef~, af04f37a HEAD from today 19th Apr 2024 (which due to not matching EEPROM product_id will be in the fall-through case of board/starfive/visionfive2/spl.c), af04f37a with applied patchset "board: starfive: add Milk-V Mars CM support" from 15th Apr 2024, and af04f37a reverting changes from e6b7aeef also with applied patchset "board: starfive: add Milk-V Mars CM support" from 15th Apr 2024. In all builds is OpenSBI at commit d4d2582e HEAD from today 19 Apr 2024. For each build tested per vendor Milk-V the Mars CM Lite (SD Card only non-eMMC) has pinmux of GPIO22 instead of GPIO62: -- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi @@ -233,7 +233,7 @@ mmc0_pins: mmc0-pins { mmc0-pins-rest { - pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST, + pinmux = <GPIOMUX(22, GPOUT_SYS_SDIO0_RST, GPOEN_ENABLE, GPI_NONE)>; bias-pull-up; drive-strength = <12>; U-Boot config is simply starfive_visionfive2_defconfig. Results are as follows. StarFive # mac --------EEPROM INFO-------- Vendor : MILK-V Product full SN: MARC-V10-2340-D004E000-000006DF data version: 0x2 PCB revision: 0xc1 BOM revision: A Ethernet MAC0 address: 6c:cf:39:00:83:11 Ethernet MAC1 address: 6c:cf:39:00:83:12 --------EEPROM INFO-------- e6b7aeef: 2GB microSD (no speed class markings) af04f37a: 2GB microSD (no speed class markings) af04f37a with Mars CM patchset: 2GB microSD (no speed class markings) StarFive # mmc rescan ; mmc info unable to select a mode unable to select a mode e6b7aeef~: 2GB microSD (no speed class markings) af04f37a revert e6b7aeef with Mars CM patchset: 2GB microSD (no speed class markings) StarFive # mmc rescan ; mmc info Device: mmc@16010000 Manufacturer ID: 1c OEM: 5356 Name: USD Bus Speed: 50000000 Mode: SD High Speed (50MHz) Rd Block Len: 512 SD version 2.0 High Capacity: No Capacity: 1.9 GiB Bus Width: 1-bit Erase Group Size: 512 Bytes e6b7aeef: 8GB microSD Class 4 e6b7aeef~: 8GB microSD Class 4 af04f37a: 8GB microSD Class 4 af04f37a with Mars CM patchset: 8GB microSD Class 4 af04f37a revert e6b7aeef with Mars CM patchset: 8GB microSD Class 4 StarFive # mmc rescan ; mmc info Device: mmc@16010000 Manufacturer ID: 2 OEM: 544d Name: SA08G Bus Speed: 50000000 Mode: SD High Speed (50MHz) Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 7.4 GiB Bus Width: 1-bit Erase Group Size: 512 Bytes e6b7aeef: 8GB microSD Class 10 e6b7aeef~: 8GB microSD Class 10 af04f37a: 8GB microSD Class 10 af04f37a with Mars CM patchset: 8GB microSD Class 10 af04f37a revert e6b7aeef with Mars CM patchset: 8GB microSD Class 10 StarFive # mmc rescan ; mmc info Device: mmc@16010000 Manufacturer ID: 74 OEM: 4a60 Name: USD Bus Speed: 50000000 Mode: SD High Speed (50MHz) Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 7.5 GiB Bus Width: 1-bit Erase Group Size: 512 Bytes e6b7aeef: 32GB microSD Class 10 A1 U1 HC1 e6b7aeef~: 32GB microSD Class 10 A1 U1 HC1 af04f37a: 32GB microSD Class 10 A1 U1 HC1 af04f37a with Mars CM patchset: 32GB microSD Class 10 A1 U1 HC1 af04f37a revert e6b7aeef with Mars CM patchset: 32GB microSD Class 10 A1 U1 HC1 StarFive # mmc rescan ; mmc info Device: mmc@16010000 Manufacturer ID: 3 OEM: 5344 Name: SC32G Bus Speed: 50000000 Mode: SD High Speed (50MHz) Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 29.7 GiB Bus Width: 1-bit Erase Group Size: 512 Bytes e6b7aeef: 200GB microSD Class 10 A1 U1 XC1 e6b7aeef~: 200GB microSD Class 10 A1 U1 XC1 af04f37a: 200GB microSD Class 10 A1 U1 XC1 af04f37a with Mars CM patchset: 200GB microSD Class 10 A1 U1 XC1 af04f37a revert e6b7aeef with Mars CM patchset: 200GB microSD Class 10 A1 U1 XC1 StarFive # mmc rescan ; mmc info Device: mmc@16010000 Manufacturer ID: 3 OEM: 5344 Name: SC200 Bus Speed: 50000000 Mode: SD High Speed (50MHz) Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 183.3 GiB Bus Width: 1-bit Erase Group Size: 512 Bytes e6b7aeef: 256GB microSD Class U3 XC1 e6b7aeef~: 256GB microSD Class U3 XC1 af04f37a: 256GB microSD Class U3 XC1 af04f37a with Mars CM patchset: 256GB microSD Class U3 XC1 af04f37a revert e6b7aeef with Mars CM patchset: 256GB microSD Class U3 XC1 StarFive # mmc rescan ; mmc info Device: mmc@16010000 Manufacturer ID: 1b OEM: 534d Name: GE4S5 Bus Speed: 50000000 Mode: SD High Speed (50MHz) Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 238.8 GiB Bus Width: 1-bit Erase Group Size: 512 Bytes > One potential problem I > could think of is perhaps the SPL built is without SPL_PINCTRL_STARFIVE/JH7110 > or the u-boot dts is missing the pinctrl that properly sets drive-strength and > other properties of the mmc0/1 pins. What dtb are you using? I tested this with > visionfive2 and it's working fine. Can you share the tree/config you used to > built for Milk-V Mars CM Lite? I don't see the corresponding dts being checked- > in to u-boot tree, so it helps if you can share the code. Thanks! > > Bo As described, this is upstream U-Boot. Does this 'mmc info' testing help give some ideas to suggest? -E
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index 2f560e7..c09d5c9 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -93,6 +93,10 @@ bootph-pre-ram; }; +&pllclk { + bootph-pre-ram; +}; + &S7_0 { status = "okay"; };
Previously PLL node was missing from SPL dts. This caused BUS_ROOT to stay on OSC clock (24Mhz). As a result, all peripherals have to run at a much lower frequency, and loading from sdcard/emmc is slow. Thus, enabling PLL node in dts to fix this. Signed-off-by: Bo Gan <ganboing@gmail.com> --- arch/riscv/dts/jh7110-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)