| Message ID | 1574347736-14222-1-git-send-email-joyce.ooi@intel.com |
|---|---|
| State | Accepted, archived |
| Commit | 7dad444c765ab94bf70592c502df9d1e1f72d436 |
| Delegated to: | Simon Goldschmidt |
| Headers | show |
| Series | [U-Boot] arm: dts: Stratix10: change pad skew values for EMAC0 PHY driver | expand |
> -----Original Message----- > From: Ooi, Joyce <joyce.ooi@intel.com> > Sent: Thursday, November 21, 2019 10:49 PM > To: Tan, Ley Foon <ley.foon.tan@intel.com>; Ang, Chee Hong > <chee.hong.ang@intel.com> > Cc: Ooi, Joyce <joyce.ooi@intel.com>; u-boot@lists.denx.de > Subject: [PATCH] arm: dts: Stratix10: change pad skew values for EMAC0 PHY > driver > > The HPS EMAC0 drive strength is changed to 4mA because the initial 8mA > drive strength has caused CE test to fail. This requires changes on the pad > skew for EMAC0 PHY driver. Based on several measurements done, Tx clock > does not require the extra 0.96ns delay which was needed in Arria10. > > Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Regards Ley Foon
On 11/22/19 2:34 AM, Tan, Ley Foon wrote: > > >> -----Original Message----- >> From: Ooi, Joyce <joyce.ooi@intel.com> >> Sent: Thursday, November 21, 2019 10:49 PM >> To: Tan, Ley Foon <ley.foon.tan@intel.com>; Ang, Chee Hong >> <chee.hong.ang@intel.com> >> Cc: Ooi, Joyce <joyce.ooi@intel.com>; u-boot@lists.denx.de >> Subject: [PATCH] arm: dts: Stratix10: change pad skew values for EMAC0 PHY >> driver >> >> The HPS EMAC0 drive strength is changed to 4mA because the initial 8mA >> drive strength has caused CE test to fail. This requires changes on the pad >> skew for EMAC0 PHY driver. Based on several measurements done, Tx clock >> does not require the extra 0.96ns delay which was needed in Arria10. >> >> Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com> > Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Applied, thanks.
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index 8c7b422..b7b48a5 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -74,7 +74,7 @@ rxd2-skew-ps = <420>; /* 0ps */ rxd3-skew-ps = <420>; /* 0ps */ txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <1860>; /* 960ps */ + txc-skew-ps = <900>; /* 0ps */ rxdv-skew-ps = <420>; /* 0ps */ rxc-skew-ps = <1680>; /* 780ps */ };
The HPS EMAC0 drive strength is changed to 4mA because the initial 8mA drive strength has caused CE test to fail. This requires changes on the pad skew for EMAC0 PHY driver. Based on several measurements done, Tx clock does not require the extra 0.96ns delay which was needed in Arria10. Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com> --- arch/arm/dts/socfpga_stratix10_socdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)