| Message ID | 1574347325-13919-1-git-send-email-joyce.ooi@intel.com |
|---|---|
| State | Deferred |
| Headers | show |
| Series | [U-Boot] spi: cadence_qspi_apb: fix QSPI write issues | expand |
> -----Original Message----- > From: Ooi, Joyce <joyce.ooi@intel.com> > Sent: Thursday, November 21, 2019 10:42 PM > To: Jagan Teki <jagan@amarulasolutions.com> > Cc: Tan, Ley Foon <ley.foon.tan@intel.com>; Ang, Chee Hong > <chee.hong.ang@intel.com>; Ooi, Joyce <joyce.ooi@intel.com>; u- > boot@lists.denx.de > Subject: [PATCH] spi: cadence_qspi_apb: fix QSPI write issues > > From: Chee Hong Ang <chee.hong.ang@intel.com> > > QSPI driver perform chip select on every flash read/write access. The driver > need to disable/enable the QSPI controller while performing chip select. This > may cause some data lost especially the QSPI controller is configured to run > at slower speed as it may take longer time to access the flash device. > This patch prevent the driver from disable/enable the QSPI controller too > soon and inadvertently halting any ongoing flash read/write access by > ensuring the QSPI controller is always in idle mode after each read/write > access. > > Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> > Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> > --- > drivers/spi/cadence_qspi_apb.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c > index 55a7501..ab14a5f 100644 > --- a/drivers/spi/cadence_qspi_apb.c > +++ b/drivers/spi/cadence_qspi_apb.c > @@ -676,6 +676,10 @@ int > cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, > writel(CQSPI_REG_INDIRECTRD_DONE, > plat->regbase + CQSPI_REG_INDIRECTRD); > > + /* Wait til QSPI is idle */ > + if (!cadence_qspi_wait_idle(plat->regbase)) > + return -EIO; > + > return 0; > > failrd: > @@ -782,6 +786,11 @@ int > cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata > *plat, > plat->regbase + CQSPI_REG_INDIRECTWR); > if (bounce_buf) > free(bounce_buf); > + > + /* Wait til QSPI is idle */ > + if (!cadence_qspi_wait_idle(plat->regbase)) > + return -EIO; > + > return 0; > > failwr: > -- > 1.9.1
Am 22.11.2019 um 03:03 schrieb Tan, Ley Foon: > > >> -----Original Message----- >> From: Ooi, Joyce <joyce.ooi@intel.com> >> Sent: Thursday, November 21, 2019 10:42 PM >> To: Jagan Teki <jagan@amarulasolutions.com> >> Cc: Tan, Ley Foon <ley.foon.tan@intel.com>; Ang, Chee Hong >> <chee.hong.ang@intel.com>; Ooi, Joyce <joyce.ooi@intel.com>; u- >> boot@lists.denx.de >> Subject: [PATCH] spi: cadence_qspi_apb: fix QSPI write issues >> >> From: Chee Hong Ang <chee.hong.ang@intel.com> >> >> QSPI driver perform chip select on every flash read/write access. The driver >> need to disable/enable the QSPI controller while performing chip select. This >> may cause some data lost especially the QSPI controller is configured to run >> at slower speed as it may take longer time to access the flash device. >> This patch prevent the driver from disable/enable the QSPI controller too >> soon and inadvertently halting any ongoing flash read/write access by >> ensuring the QSPI controller is always in idle mode after each read/write >> access. >> >> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> >> Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com> > > Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> > >> --- >> drivers/spi/cadence_qspi_apb.c | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c >> index 55a7501..ab14a5f 100644 >> --- a/drivers/spi/cadence_qspi_apb.c >> +++ b/drivers/spi/cadence_qspi_apb.c >> @@ -676,6 +676,10 @@ int >> cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, >> writel(CQSPI_REG_INDIRECTRD_DONE, >> plat->regbase + CQSPI_REG_INDIRECTRD); >> >> + /* Wait til QSPI is idle */ >> + if (!cadence_qspi_wait_idle(plat->regbase)) >> + return -EIO; >> + >> return 0; >> >> failrd: >> @@ -782,6 +786,11 @@ int >> cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata >> *plat, >> plat->regbase + CQSPI_REG_INDIRECTWR); >> if (bounce_buf) >> free(bounce_buf); >> + >> + /* Wait til QSPI is idle */ >> + if (!cadence_qspi_wait_idle(plat->regbase)) >> + return -EIO; >> + >> return 0; >> >> failwr: >> -- >> 1.9.1 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot >
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 55a7501..ab14a5f 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -676,6 +676,10 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, writel(CQSPI_REG_INDIRECTRD_DONE, plat->regbase + CQSPI_REG_INDIRECTRD); + /* Wait til QSPI is idle */ + if (!cadence_qspi_wait_idle(plat->regbase)) + return -EIO; + return 0; failrd: @@ -782,6 +786,11 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, plat->regbase + CQSPI_REG_INDIRECTWR); if (bounce_buf) free(bounce_buf); + + /* Wait til QSPI is idle */ + if (!cadence_qspi_wait_idle(plat->regbase)) + return -EIO; + return 0; failwr: