| Message ID | 1505302336-74720-1-git-send-email-david.wu@rock-chips.com |
|---|---|
| State | Superseded |
| Delegated to: | Philipp Tomsich |
| Headers | show |
| Series | Add rockchip Saradc support | expand |
> The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). > Saradc integer divider control register is 8-bits width. > > Signed-off-by: David Wu <david.wu@rock-chips.com> > --- > arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 5 ++++ > drivers/clk/rockchip/clk_rk3368.c | 32 +++++++++++++++++++++++++ > 2 files changed, 37 insertions(+) > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
On Wed, 13 Sep 2017, David Wu wrote: > The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). > Saradc integer divider control register is 8-bits width. > > Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> See below for comments. > --- > arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 5 ++++ > drivers/clk/rockchip/clk_rk3368.c | 32 +++++++++++++++++++++++++ > 2 files changed, 37 insertions(+) > > diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h > index 2b1197f..31f7685 100644 > --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h > +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h > @@ -89,6 +89,11 @@ enum { > MCU_CLK_DIV_SHIFT = 0, > MCU_CLK_DIV_MASK = GENMASK(4, 0), > > + /* CLKSEL_CON25 */ > + CLK_SARADC_DIV_CON_SHIFT = 8, > + CLK_SARADC_DIV_CON_MASK = 0xff << CLK_SARADC_DIV_CON_SHIFT, Please use GENMASK. > + CLK_SARADC_DIV_CON_WIDTH = 8, > + > /* CLKSEL43_CON */ > GMAC_MUX_SEL_EXTCLK = BIT(8), > > diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c > index 2be1f57..2eedf77 100644 > --- a/drivers/clk/rockchip/clk_rk3368.c > +++ b/drivers/clk/rockchip/clk_rk3368.c > @@ -12,6 +12,7 @@ > #include <errno.h> > #include <mapmem.h> > #include <syscon.h> > +#include <bitfield.h> > #include <asm/arch/clock.h> > #include <asm/arch/cru_rk3368.h> > #include <asm/arch/hardware.h> > @@ -397,6 +398,31 @@ static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz) > return rk3368_spi_get_clk(cru, clk_id); > } > > +static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru) > +{ > + u32 div, val; > + > + val = readl(&cru->clksel_con[25]); > + div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, > + CLK_SARADC_DIV_CON_WIDTH); Please reuse the functions from bitfield.h. > + > + return DIV_TO_RATE(OSC_HZ, div); > +} > + > +static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz) > +{ > + int src_clk_div; > + > + src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; > + assert(src_clk_div < 128); > + > + rk_clrsetreg(&cru->clksel_con[25], > + CLK_SARADC_DIV_CON_MASK, > + src_clk_div << CLK_SARADC_DIV_CON_SHIFT); > + > + return rk3368_saradc_get_clk(cru); > +} > + > static ulong rk3368_clk_get_rate(struct clk *clk) > { > struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); > @@ -419,6 +445,9 @@ static ulong rk3368_clk_get_rate(struct clk *clk) > rate = rk3368_mmc_get_clk(priv->cru, clk->id); > break; > #endif > + case SCLK_SARADC: > + rate = rk3368_saradc_get_clk(priv->cru); > + break; > default: > return -ENOENT; > } > @@ -453,6 +482,9 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) > ret = rk3368_gmac_set_clk(priv->cru, clk->id, rate); > break; > #endif > + case SCLK_SARADC: > + ret = rk3368_saradc_set_clk(priv->cru, rate); > + break; > default: > return -ENOENT; > } >
> On 13 Sep 2017, at 22:41, Philipp Tomsich <philipp.tomsich@theobroma-systems.com> wrote: > > > > On Wed, 13 Sep 2017, David Wu wrote: > >> The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). >> Saradc integer divider control register is 8-bits width. >> >> Signed-off-by: David Wu <david.wu@rock-chips.com <mailto:david.wu@rock-chips.com>> > > Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com <mailto:philipp.tomsich@theobroma-systems.com>> > > See below for comments. > >> --- >> arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 5 ++++ >> drivers/clk/rockchip/clk_rk3368.c | 32 +++++++++++++++++++++++++ >> 2 files changed, 37 insertions(+) >> >> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h >> index 2b1197f..31f7685 100644 >> --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h >> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h >> @@ -89,6 +89,11 @@ enum { >> MCU_CLK_DIV_SHIFT = 0, >> MCU_CLK_DIV_MASK = GENMASK(4, 0), >> >> + /* CLKSEL_CON25 */ >> + CLK_SARADC_DIV_CON_SHIFT = 8, >> + CLK_SARADC_DIV_CON_MASK = 0xff << CLK_SARADC_DIV_CON_SHIFT, > > Please use GENMASK. > >> + CLK_SARADC_DIV_CON_WIDTH = 8, >> + >> /* CLKSEL43_CON */ >> GMAC_MUX_SEL_EXTCLK = BIT(8), >> >> diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c >> index 2be1f57..2eedf77 100644 >> --- a/drivers/clk/rockchip/clk_rk3368.c >> +++ b/drivers/clk/rockchip/clk_rk3368.c >> @@ -12,6 +12,7 @@ >> #include <errno.h> >> #include <mapmem.h> >> #include <syscon.h> >> +#include <bitfield.h> >> #include <asm/arch/clock.h> >> #include <asm/arch/cru_rk3368.h> >> #include <asm/arch/hardware.h> >> @@ -397,6 +398,31 @@ static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz) >> return rk3368_spi_get_clk(cru, clk_id); >> } >> >> +static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru) >> +{ >> + u32 div, val; >> + >> + val = readl(&cru->clksel_con[25]); >> + div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, >> + CLK_SARADC_DIV_CON_WIDTH); > > Please reuse the functions from bitfield.h. It’s apparently too late to do code reviews: please ignore this comment. > >> + >> + return DIV_TO_RATE(OSC_HZ, div); >> +} >> + >> +static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz) >> +{ >> + int src_clk_div; >> + >> + src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; >> + assert(src_clk_div < 128); >> + >> + rk_clrsetreg(&cru->clksel_con[25], >> + CLK_SARADC_DIV_CON_MASK, >> + src_clk_div << CLK_SARADC_DIV_CON_SHIFT); >> + >> + return rk3368_saradc_get_clk(cru); >> +} >> + >> static ulong rk3368_clk_get_rate(struct clk *clk) >> { >> struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); >> @@ -419,6 +445,9 @@ static ulong rk3368_clk_get_rate(struct clk *clk) >> rate = rk3368_mmc_get_clk(priv->cru, clk->id); >> break; >> #endif >> + case SCLK_SARADC: >> + rate = rk3368_saradc_get_clk(priv->cru); >> + break; >> default: >> return -ENOENT; >> } >> @@ -453,6 +482,9 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) >> ret = rk3368_gmac_set_clk(priv->cru, clk->id, rate); >> break; >> #endif >> + case SCLK_SARADC: >> + ret = rk3368_saradc_set_clk(priv->cru, rate); >> + break; >> default: >> return -ENOENT; >> }
> On 14 Sep 2017, at 13:17, David.Wu <david.wu@rock-chips.com> wrote: > > Hi Philipp, > > 在 2017/9/14 4:41, Philipp Tomsich 写道: >>> +static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru) >>> +{ >>> + u32 div, val; >>> + >>> + val = readl(&cru->clksel_con[25]); >>> + div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, >>> + CLK_SARADC_DIV_CON_WIDTH); >> Please reuse the functions from bitfield.h. > > Ah, the bitfield_extract function is from bitfield.h here. > I was suffering from a lack of sleep yesterday, so just ignore this comment of mine. —Phil.
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h index 2b1197f..31f7685 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h @@ -89,6 +89,11 @@ enum { MCU_CLK_DIV_SHIFT = 0, MCU_CLK_DIV_MASK = GENMASK(4, 0), + /* CLKSEL_CON25 */ + CLK_SARADC_DIV_CON_SHIFT = 8, + CLK_SARADC_DIV_CON_MASK = 0xff << CLK_SARADC_DIV_CON_SHIFT, + CLK_SARADC_DIV_CON_WIDTH = 8, + /* CLKSEL43_CON */ GMAC_MUX_SEL_EXTCLK = BIT(8), diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 2be1f57..2eedf77 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -12,6 +12,7 @@ #include <errno.h> #include <mapmem.h> #include <syscon.h> +#include <bitfield.h> #include <asm/arch/clock.h> #include <asm/arch/cru_rk3368.h> #include <asm/arch/hardware.h> @@ -397,6 +398,31 @@ static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz) return rk3368_spi_get_clk(cru, clk_id); } +static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru) +{ + u32 div, val; + + val = readl(&cru->clksel_con[25]); + div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, + CLK_SARADC_DIV_CON_WIDTH); + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz) +{ + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; + assert(src_clk_div < 128); + + rk_clrsetreg(&cru->clksel_con[25], + CLK_SARADC_DIV_CON_MASK, + src_clk_div << CLK_SARADC_DIV_CON_SHIFT); + + return rk3368_saradc_get_clk(cru); +} + static ulong rk3368_clk_get_rate(struct clk *clk) { struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); @@ -419,6 +445,9 @@ static ulong rk3368_clk_get_rate(struct clk *clk) rate = rk3368_mmc_get_clk(priv->cru, clk->id); break; #endif + case SCLK_SARADC: + rate = rk3368_saradc_get_clk(priv->cru); + break; default: return -ENOENT; } @@ -453,6 +482,9 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) ret = rk3368_gmac_set_clk(priv->cru, clk->id, rate); break; #endif + case SCLK_SARADC: + ret = rk3368_saradc_set_clk(priv->cru, rate); + break; default: return -ENOENT; }
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). Saradc integer divider control register is 8-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> --- arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 5 ++++ drivers/clk/rockchip/clk_rk3368.c | 32 +++++++++++++++++++++++++ 2 files changed, 37 insertions(+)