| Message ID | 1500410199-13039-46-git-send-email-philipp.tomsich@theobroma-systems.com |
|---|---|
| State | Superseded |
| Delegated to: | Philipp Tomsich |
| Headers | show |
Hi Philipp: On 2017年07月19日 04:36, Philipp Tomsich wrote: > For full SPL support, including DRAM initialisation, we need a few > nodes from the DTS: this commit adds the DMC (DRAM controller) node, > the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU > as 'u-boot,dm-pre-reloc'. In addition to this, we also include the > dt-binding for the DMC to allow DTS files including this DTSI to refer > to the symbolic constants for the DDR3 bin and for the > memory-schedule. > > Note that the DMC contains both the memory regions for the > (Designware) protocol controller as well as the DDR PHY. > > Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > --- > > arch/arm/dts/rk3368.dtsi | 26 ++++++++++++++++++++------ > 1 file changed, 20 insertions(+), 6 deletions(-) > > diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi > index 9daf765..8dd6549 100644 > --- a/arch/arm/dts/rk3368.dtsi > +++ b/arch/arm/dts/rk3368.dtsi > @@ -46,6 +46,7 @@ > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/pinctrl/rockchip.h> > #include <dt-bindings/thermal/thermal.h> > +#include <dt-bindings/memory/rk3368-dmc.h> > > / { > compatible = "rockchip,rk3368"; > @@ -227,6 +228,23 @@ > #clock-cells = <0>; > }; > > + dmc: dmc@ff610000 { > + u-boot,dm-pre-reloc; > + compatible = "rockchip,rk3368-dmc", "syscon"; > + rockchip,cru = <&cru>; > + rockchip,grf = <&grf>; > + rockchip,msch = <&service_msch>; > + reg = <0 0xff610000 0 0x400 > + 0 0xff620000 0 0x400>; > + }; > + > + service_msch: syscon@ffac0000 { > + u-boot,dm-pre-reloc; > + compatible = "rockchip,rk3368-msch", "syscon"; > + reg = <0x0 0xffac0000 0x0 0x2000>; > + status = "okay"; > + }; > + > sdmmc: dwmmc@ff0c0000 { > compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; > reg = <0x0 0xff0c0000 0x0 0x4000>; > @@ -546,12 +564,6 @@ > status = "disabled"; > }; > > - dmc: dmc@ff610000 { > - u-boot,dm-pre-reloc; > - compatible = "rockchip,rk3368-dmc", "syscon"; > - reg = <0x0 0xff610000 0x0 0x1000>; > - }; > - > i2c0: i2c@ff650000 { > compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; > reg = <0x0 0xff650000 0x0 0x1000>; > @@ -653,6 +665,7 @@ > }; > > cru: clock-controller@ff760000 { > + u-boot,dm-pre-reloc; As U-BOOT has introduced xxx-u-boot.dtsi for the U-BOOT-spceific dt information. I think it's better to put this u-boot needed things in rk3368-u-boot.dtsi. It will make things easier when we need to sync the dts with upstream kernel. > compatible = "rockchip,rk3368-cru"; > reg = <0x0 0xff760000 0x0 0x1000>; > rockchip,grf = <&grf>; > @@ -661,6 +674,7 @@ > }; > > grf: syscon@ff770000 { > + u-boot,dm-pre-reloc; > compatible = "rockchip,rk3368-grf", "syscon"; > reg = <0x0 0xff770000 0x0 0x1000>; > };
diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi index 9daf765..8dd6549 100644 --- a/arch/arm/dts/rk3368.dtsi +++ b/arch/arm/dts/rk3368.dtsi @@ -46,6 +46,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/memory/rk3368-dmc.h> / { compatible = "rockchip,rk3368"; @@ -227,6 +228,23 @@ #clock-cells = <0>; }; + dmc: dmc@ff610000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3368-dmc", "syscon"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,msch = <&service_msch>; + reg = <0 0xff610000 0 0x400 + 0 0xff620000 0 0x400>; + }; + + service_msch: syscon@ffac0000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3368-msch", "syscon"; + reg = <0x0 0xffac0000 0x0 0x2000>; + status = "okay"; + }; + sdmmc: dwmmc@ff0c0000 { compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0c0000 0x0 0x4000>; @@ -546,12 +564,6 @@ status = "disabled"; }; - dmc: dmc@ff610000 { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3368-dmc", "syscon"; - reg = <0x0 0xff610000 0x0 0x1000>; - }; - i2c0: i2c@ff650000 { compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; reg = <0x0 0xff650000 0x0 0x1000>; @@ -653,6 +665,7 @@ }; cru: clock-controller@ff760000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3368-cru"; reg = <0x0 0xff760000 0x0 0x1000>; rockchip,grf = <&grf>; @@ -661,6 +674,7 @@ }; grf: syscon@ff770000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3368-grf", "syscon"; reg = <0x0 0xff770000 0x0 0x1000>; };
For full SPL support, including DRAM initialisation, we need a few nodes from the DTS: this commit adds the DMC (DRAM controller) node, the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU as 'u-boot,dm-pre-reloc'. In addition to this, we also include the dt-binding for the DMC to allow DTS files including this DTSI to refer to the symbolic constants for the DDR3 bin and for the memory-schedule. Note that the DMC contains both the memory regions for the (Designware) protocol controller as well as the DDR PHY. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> --- arch/arm/dts/rk3368.dtsi | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-)