| Message ID | 1498213779-25340-1-git-send-email-priyanka.jain@nxp.com |
|---|---|
| State | Superseded |
| Delegated to: | York Sun |
| Headers | show |
On 06/23/2017 03:30 AM, Priyanka Jain wrote: > Update MC address caluclation as per MC design requirement > of address as least significant 512MB address > of MC private allocated memory. > > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> > Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> > --- > drivers/net/fsl-mc/mc.c | 7 ++++++- > 1 files changed, 6 insertions(+), 1 deletions(-) > > diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c > index eeecb2d..623586c 100644 > --- a/drivers/net/fsl-mc/mc.c > +++ b/drivers/net/fsl-mc/mc.c > @@ -704,10 +704,15 @@ int get_dpl_apply_status(void) > > /** > * Return the MC address of private DRAM block. > + * MC address should be least significant 512MB address > + * of MC private memory > */ > u64 mc_get_dram_addr(void) > { > - return gd->arch.resv_ram; > + size_t mc_ram_size = mc_get_dram_block_size(); > + > + return (gd->arch.resv_ram + mc_ram_size - 1) & > + MC_RAM_BASE_ADDR_ALIGNMENT_MASK; > } > > /** > Priyanka, This looks odd. You already have the address aligned by CONFIG_SYS_MC_RSV_MEM_ALIGN (512MB by default), tracked by gd->arch.resv_ram. Did you find the address is wrong sometimes? York
> -----Original Message----- > From: York Sun > Sent: Wednesday, August 09, 2017 10:19 PM > To: Priyanka Jain <priyanka.jain@nxp.com>; u-boot@lists.denx.de > Cc: Ashish Kumar <ashish.kumar@nxp.com> > Subject: Re: [PATCH] drivers:net:fsl-mc: Update MC address calculation > > On 06/23/2017 03:30 AM, Priyanka Jain wrote: > > Update MC address caluclation as per MC design requirement of address > > as least significant 512MB address of MC private allocated memory. > > > > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> > > Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> > > --- > > drivers/net/fsl-mc/mc.c | 7 ++++++- > > 1 files changed, 6 insertions(+), 1 deletions(-) > > > > diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index > > eeecb2d..623586c 100644 > > --- a/drivers/net/fsl-mc/mc.c > > +++ b/drivers/net/fsl-mc/mc.c > > @@ -704,10 +704,15 @@ int get_dpl_apply_status(void) > > > > /** > > * Return the MC address of private DRAM block. > > + * MC address should be least significant 512MB address > > + * of MC private memory > > */ > > u64 mc_get_dram_addr(void) > > { > > - return gd->arch.resv_ram; > > + size_t mc_ram_size = mc_get_dram_block_size(); > > + > > + return (gd->arch.resv_ram + mc_ram_size - 1) & > > + MC_RAM_BASE_ADDR_ALIGNMENT_MASK; > > } > > > > /** > > > > Priyanka, > > This looks odd. You already have the address aligned by > CONFIG_SYS_MC_RSV_MEM_ALIGN (512MB by default), tracked by > gd->arch.resv_ram. Did you find the address is wrong sometimes? > > York York, As per MC design requirement, MC memory should be 512MB aligned for which start address is gd->arch.resv_ram. But the MC core's initial boot address should not contain start address. It must be located in the least significant 512MB of its address range. So this change is basically shifting address from start of memory towards end of Memory (which is least significant 512MB address). Priyanka
On 08/10/2017 10:46 PM, Priyanka Jain wrote: > >> -----Original Message----- >> From: York Sun >> Sent: Wednesday, August 09, 2017 10:19 PM >> To: Priyanka Jain <priyanka.jain@nxp.com>; u-boot@lists.denx.de >> Cc: Ashish Kumar <ashish.kumar@nxp.com> >> Subject: Re: [PATCH] drivers:net:fsl-mc: Update MC address calculation >> >> On 06/23/2017 03:30 AM, Priyanka Jain wrote: >>> Update MC address caluclation as per MC design requirement of address >>> as least significant 512MB address of MC private allocated memory. >>> >>> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> >>> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> >>> --- >>> drivers/net/fsl-mc/mc.c | 7 ++++++- >>> 1 files changed, 6 insertions(+), 1 deletions(-) >>> >>> diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index >>> eeecb2d..623586c 100644 >>> --- a/drivers/net/fsl-mc/mc.c >>> +++ b/drivers/net/fsl-mc/mc.c >>> @@ -704,10 +704,15 @@ int get_dpl_apply_status(void) >>> >>> /** >>> * Return the MC address of private DRAM block. >>> + * MC address should be least significant 512MB address >>> + * of MC private memory >>> */ >>> u64 mc_get_dram_addr(void) >>> { >>> - return gd->arch.resv_ram; >>> + size_t mc_ram_size = mc_get_dram_block_size(); >>> + >>> + return (gd->arch.resv_ram + mc_ram_size - 1) & >>> + MC_RAM_BASE_ADDR_ALIGNMENT_MASK; >>> } >>> >>> /** >>> >> >> Priyanka, >> >> This looks odd. You already have the address aligned by >> CONFIG_SYS_MC_RSV_MEM_ALIGN (512MB by default), tracked by >> gd->arch.resv_ram. Did you find the address is wrong sometimes? >> >> York > > York, > > As per MC design requirement, MC memory should be 512MB aligned for which start address is gd->arch.resv_ram. > But the MC core’s initial boot address should not contain start address. It must be located in the least significant 512MB of its address range. > So this change is basically shifting address from start of memory towards end of Memory (which is least significant 512MB address). > Priyanka, You confused me. The reserved memory tracked by gd->arch.resv_ram is the beginning of the memory, aligned to 512MB (CONFIG_SYS_MC_RSV_MEM_ALIGN). It is naturally the lowest address in the reserved block. Isn't it "least significant"? If this involves complicated address allocation, please follow up with me for in-depth internal discussion. York
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index eeecb2d..623586c 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -704,10 +704,15 @@ int get_dpl_apply_status(void) /** * Return the MC address of private DRAM block. + * MC address should be least significant 512MB address + * of MC private memory */ u64 mc_get_dram_addr(void) { - return gd->arch.resv_ram; + size_t mc_ram_size = mc_get_dram_block_size(); + + return (gd->arch.resv_ram + mc_ram_size - 1) & + MC_RAM_BASE_ADDR_ALIGNMENT_MASK; } /**