diff mbox

[U-Boot,v4,05/19] arm: socfpga: Add A10 macros

Message ID 1491384774-49629-6-git-send-email-ley.foon.tan@intel.com
State Superseded
Delegated to: Marek Vasut
Headers show

Commit Message

Ley Foon Tan April 5, 2017, 9:32 a.m. UTC
Add i2c, timer and other A10 macros.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

Comments

Dinh Nguyen April 6, 2017, 2:10 p.m. UTC | #1
On Wed, Apr 5, 2017 at 4:32 AM, Ley Foon Tan <ley.foon.tan@intel.com> wrote:
> Add i2c, timer and other A10 macros.
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
>  arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> index a7056d4..448fbdc 100644
> --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright (C) 2014 Altera Corporation <www.altera.com>
> + * Copyright (C) 2014-2017 Altera Corporation <www.altera.com>
>   *
>   * SPDX-License-Identifier:    GPL-2.0+
>   */
> @@ -29,14 +29,20 @@
>  #define SOCFPGA_MPUL2_ADDRESS                  0xfffff000
>  #define SOCFPGA_I2C0_ADDRESS                   0xffc02200
>  #define SOCFPGA_I2C1_ADDRESS                   0xffc02300
> +#define SOCFPGA_I2C2_ADDRESS                   0xffc02400
> +#define SOCFPGA_I2C3_ADDRESS                   0xffc02500
> +#define SOCFPGA_I2C4_ADDRESS                   0xffc02600

I made this comment in V3, and I'll make it again. Do we need to add
these when we can use DTS for the I2C driver?

Dinh
Ley Foon Tan April 7, 2017, 12:32 a.m. UTC | #2
On Thu, Apr 6, 2017 at 10:10 PM, Dinh Nguyen <dinh.linux@gmail.com> wrote:
> On Wed, Apr 5, 2017 at 4:32 AM, Ley Foon Tan <ley.foon.tan@intel.com> wrote:
>> Add i2c, timer and other A10 macros.
>>
>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>> ---
>>  arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 8 +++++++-
>>  1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
>> index a7056d4..448fbdc 100644
>> --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
>> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
>> @@ -1,5 +1,5 @@
>>  /*
>> - * Copyright (C) 2014 Altera Corporation <www.altera.com>
>> + * Copyright (C) 2014-2017 Altera Corporation <www.altera.com>
>>   *
>>   * SPDX-License-Identifier:    GPL-2.0+
>>   */
>> @@ -29,14 +29,20 @@
>>  #define SOCFPGA_MPUL2_ADDRESS                  0xfffff000
>>  #define SOCFPGA_I2C0_ADDRESS                   0xffc02200
>>  #define SOCFPGA_I2C1_ADDRESS                   0xffc02300
>> +#define SOCFPGA_I2C2_ADDRESS                   0xffc02400
>> +#define SOCFPGA_I2C3_ADDRESS                   0xffc02500
>> +#define SOCFPGA_I2C4_ADDRESS                   0xffc02600
>
> I made this comment in V3, and I'll make it again. Do we need to add
> these when we can use DTS for the I2C driver?
>
We haven't enable CONFIG_DM_I2C for i2c in this patch series, so it
still using older device model and these macros are still required in
socfpga_common.h (#define CONFIG_SYS_I2C_BASE
SOCFPGA_I2C0_ADDRESS).

Regards
Ley Foon
diff mbox

Patch

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index a7056d4..448fbdc 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -1,5 +1,5 @@ 
 /*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014-2017 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -29,14 +29,20 @@ 
 #define SOCFPGA_MPUL2_ADDRESS			0xfffff000
 #define SOCFPGA_I2C0_ADDRESS			0xffc02200
 #define SOCFPGA_I2C1_ADDRESS			0xffc02300
+#define SOCFPGA_I2C2_ADDRESS			0xffc02400
+#define SOCFPGA_I2C3_ADDRESS			0xffc02500
+#define SOCFPGA_I2C4_ADDRESS			0xffc02600
 
 #define SOCFPGA_ECC_OCRAM_ADDRESS		0xff8c3000
 #define SOCFPGA_UART0_ADDRESS			0xffc02000
 #define SOCFPGA_OSC1TIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_OSC1TIMER1_ADDRESS		0xffd00100
 #define SOCFPGA_CLKMGR_ADDRESS			0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS			0xffd05000
 
 #define SOCFPGA_SDR_ADDRESS			0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST		0xffd11000
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST		0xffd13500
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xffd12400
 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS	0xffd13200
 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS	0xffd13300