[U-Boot,v1] sun8i_emac: configure PHY reset GPIO via DM

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 5094dd8..664d585 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -1,98 +1,101 @@ 
 /*
  * (C) Copyright 2016
  * Author: Amit Singh Tomar, amittomer25@gmail.com
  *
  * SPDX-License-Identifier:     GPL-2.0+
  *
  * Ethernet driver for H3/A64/A83T based SoC's
  *
  * It is derived from the work done by
  * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
  *
 */
 
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
 #include <common.h>
 #include <dm.h>
 #include <fdt_support.h>
 #include <linux/err.h>
 #include <malloc.h>
 #include <miiphy.h>
 #include <net.h>
+#ifdef CONFIG_DM_GPIO
+#include <asm-generic/gpio.h>
+#endif
 
 #define MDIO_CMD_MII_BUSY		BIT(0)
 #define MDIO_CMD_MII_WRITE		BIT(1)
 
 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK	0x000001f0
 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT	4
 #define MDIO_CMD_MII_PHY_ADDR_MASK	0x0001f000
 #define MDIO_CMD_MII_PHY_ADDR_SHIFT	12
 
 #define MDIO_CMD_MDC_DIV_RATIO_M_SHIFT  20
 #define MDIO_CMD_MDC_DIV_16             (0 << MDIO_CMD_MDC_DIV_RATIO_M_SHIFT)
 #define MDIO_CMD_MDC_DIV_32             (1 << MDIO_CMD_MDC_DIV_RATIO_M_SHIFT)
 #define MDIO_CMD_MDC_DIV_64             (2 << MDIO_CMD_MDC_DIV_RATIO_M_SHIFT)
 #define MDIO_CMD_MDC_DIV_128            (3 << MDIO_CMD_MDC_DIV_RATIO_M_SHIFT)
 
 #define CONFIG_TX_DESCR_NUM	32
 #define CONFIG_RX_DESCR_NUM	32
 #define CONFIG_ETH_BUFSIZE	2048 /* Note must be dma aligned */
 
 /*
  * The datasheet says that each descriptor can transfers up to 4096 bytes
  * But later, the register documentation reduces that value to 2048,
  * using 2048 cause strange behaviours and even BSP driver use 2047
  */
 #define CONFIG_ETH_RXSIZE	2044 /* Note must fit in ETH_BUFSIZE */
 
 #define TX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
 #define RX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
 
 #define H3_EPHY_DEFAULT_VALUE	0x58000
 #define H3_EPHY_DEFAULT_MASK	GENMASK(31, 15)
 #define H3_EPHY_ADDR_SHIFT	20
 #define REG_PHY_ADDR_MASK	GENMASK(4, 0)
 #define H3_EPHY_LED_POL		BIT(17)	/* 1: active low, 0: active high */
 #define H3_EPHY_SHUTDOWN	BIT(16)	/* 1: shutdown, 0: power up */
 #define H3_EPHY_SELECT		BIT(15) /* 1: internal PHY, 0: external PHY */
 
 #define SC_RMII_EN		BIT(13)
 #define SC_EPIT			BIT(2) /* 1: RGMII, 0: MII */
 #define SC_ETCS_MASK		GENMASK(1, 0)
 #define SC_ETCS_EXT_GMII	0x1
 #define SC_ETCS_INT_GMII	0x2
 
 #define CONFIG_MDIO_TIMEOUT	(3 * CONFIG_SYS_HZ)
 
 #define AHB_GATE_OFFSET_EPHY	0
 
 #if defined(CONFIG_MACH_SUN8I_H3)
 #define SUN8I_GPD8_GMAC		2
 #else
 #define SUN8I_GPD8_GMAC		4
 #endif
 
 /* H3/A64 EMAC Register's offset */
 #define EMAC_CTL0		0x00
 #define EMAC_CTL1		0x04
 #define EMAC_INT_STA		0x08
 #define EMAC_INT_EN		0x0c
 #define EMAC_TX_CTL0		0x10
 #define EMAC_TX_CTL1		0x14
 #define EMAC_TX_FLOW_CTL	0x1c
 #define EMAC_TX_DMA_DESC	0x20
 #define EMAC_RX_CTL0		0x24
 #define EMAC_RX_CTL1		0x28
 #define EMAC_RX_DMA_DESC	0x34
 #define EMAC_MII_CMD		0x48
 #define EMAC_MII_DATA		0x4c
 #define EMAC_ADDR0_HIGH		0x50
 #define EMAC_ADDR0_LOW		0x54
 #define EMAC_TX_DMA_STA		0xb0
 #define EMAC_TX_CUR_DESC	0xb4
 #define EMAC_TX_CUR_BUF		0xb8
 #define EMAC_RX_DMA_STA		0xc0
 #define EMAC_RX_CUR_DESC	0xc4
 
@@ -114,91 +117,103 @@  struct emac_dma_desc {
 struct emac_eth_dev {
 	struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
 	struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
 	char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 	char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 
 	u32 interface;
 	u32 phyaddr;
 	u32 link;
 	u32 speed;
 	u32 duplex;
 	u32 phy_configured;
 	u32 tx_currdescnum;
 	u32 rx_currdescnum;
 	u32 addr;
 	u32 tx_slot;
 	bool use_internal_phy;
 
 	enum emac_variant variant;
 	void *mac_reg;
 	phys_addr_t sysctl_reg;
 	struct phy_device *phydev;
 	struct mii_dev *bus;
+#ifdef CONFIG_DM_GPIO
+	struct gpio_desc reset_gpio;
+#endif
+};
+
+
+struct sun8i_eth_pdata {
+	struct eth_pdata eth_pdata;
+	u32 reset_delays[3];
 };
 
+
 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 {
-	struct emac_eth_dev *priv = bus->priv;
+	struct udevice *dev = bus->priv;
+	struct emac_eth_dev *priv = dev_get_priv(dev);
 	ulong start;
 	u32 miiaddr = 0;
 	int timeout = CONFIG_MDIO_TIMEOUT;
 
 	miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
 		MDIO_CMD_MII_PHY_REG_ADDR_MASK;
 	miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
 		MDIO_CMD_MII_PHY_ADDR_MASK;
 
 	/* The MAC block is fed by a 300MHz clock, so we need to divide by 128
 	   to bring the MDC into the range permissible by the IEEE standard. */
 	miiaddr |= MDIO_CMD_MDC_DIV_128;
 
 	miiaddr |= MDIO_CMD_MII_BUSY;
 
 	writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
 
 	start = get_timer(0);
 	while (get_timer(start) < timeout) {
 		if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
 			return readl(priv->mac_reg + EMAC_MII_DATA);
 		udelay(10);
 	};
 
 	return -1;
 }
 
 static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
 			    u16 val)
 {
-	struct emac_eth_dev *priv = bus->priv;
+	struct udevice *dev = bus->priv;
+	struct emac_eth_dev *priv = dev_get_priv(dev);
 	ulong start;
 	u32 miiaddr = 0;
 	int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
 
 	miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
 		MDIO_CMD_MII_PHY_REG_ADDR_MASK;
 	miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
 		MDIO_CMD_MII_PHY_ADDR_MASK;
 
 	miiaddr |= MDIO_CMD_MII_WRITE;
 	miiaddr |= MDIO_CMD_MII_BUSY;
 
 	/* The MAC block is fed by a 300MHz clock, so we need to divide by 128
 	   to bring the MDC into the range permissible by the IEEE standard. */
 	miiaddr |= MDIO_CMD_MDC_DIV_128;
 
 	writel(val, priv->mac_reg + EMAC_MII_DATA);
 	writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
 
 	start = get_timer(0);
 	while (get_timer(start) < timeout) {
 		if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
 					MDIO_CMD_MII_BUSY)) {
 			ret = 0;
 			break;
 		}
 		udelay(10);
 	};
 
 	return ret;
 }
 
@@ -610,20 +625,57 @@  static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
 	setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
 }
 
-static int sun8i_mdio_init(const char *name, struct  emac_eth_dev *priv)
+#if defined(CONFIG_DM_GPIO)
+static int sun8i_mdio_reset(struct mii_dev *bus)
+{
+	struct udevice *dev = bus->priv;
+	struct emac_eth_dev *priv = dev_get_priv(dev);
+	struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
+	int ret;
+
+	if (!dm_gpio_is_valid(&priv->reset_gpio))
+		return 0;
+
+	/* reset the phy */
+	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	if (ret)
+		return ret;
+
+	udelay(pdata->reset_delays[0]);
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+	if (ret)
+		return ret;
+
+	udelay(pdata->reset_delays[1]);
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	if (ret)
+		return ret;
+
+	udelay(pdata->reset_delays[2]);
+
+	return 0;
+}
+#endif
+
+static int sun8i_mdio_init(const char *name, struct udevice *priv)
 {
 	struct mii_dev *bus = mdio_alloc();
 
 	if (!bus) {
 		debug("Failed to allocate MDIO bus\n");
 		return -ENOMEM;
 	}
 
 	bus->read = sun8i_mdio_read;
 	bus->write = sun8i_mdio_write;
 	snprintf(bus->name, sizeof(bus->name), name);
 	bus->priv = (void *)priv;
+#if defined(CONFIG_DM_GPIO)
+	bus->reset = sun8i_mdio_reset;
+#endif
 
 	return  mdio_register(bus);
 }
 
@@ -695,16 +747,16 @@  static void sun8i_emac_eth_stop(struct udevice *dev)
 static int sun8i_emac_eth_probe(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	struct emac_eth_dev *priv = dev_get_priv(dev);
 
 	priv->mac_reg = (void *)pdata->iobase;
 
 	sun8i_emac_board_setup(priv);
 	sun8i_emac_set_syscon(priv);
 
-	sun8i_mdio_init(dev->name, priv);
+	sun8i_mdio_init(dev->name, dev);
 	priv->bus = miiphy_get_dev_by_name(dev->name);
 
 	return sun8i_phy_init(priv, dev);
 }
 
@@ -719,55 +771,76 @@  static const struct eth_ops sun8i_emac_eth_ops = {
 
 static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
 {
-	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
+	struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
 	struct emac_eth_dev *priv = dev_get_priv(dev);
 	const char *phy_mode;
 	int node = dev_of_offset(dev);
 	int offset = 0;
+#ifdef CONFIG_DM_GPIO
+	int reset_flags = GPIOD_IS_OUT;
+	int ret = 0;
+#endif
 
 	pdata->iobase = dev_get_addr_name(dev, "emac");
 	priv->sysctl_reg = dev_get_addr_name(dev, "syscon");
 
 	pdata->phy_interface = -1;
 	priv->phyaddr = -1;
 	priv->use_internal_phy = false;
 
 	offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
 				       "phy");
 	if (offset > 0)
 		priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg",
 					       -1);
 
 	phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
 
 	if (phy_mode)
 		pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 	printf("phy interface%d\n", pdata->phy_interface);
 
 	if (pdata->phy_interface == -1) {
 		debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 		return -EINVAL;
 	}
 
 	priv->variant = dev_get_driver_data(dev);
 
 	if (!priv->variant) {
 		printf("%s: Missing variant '%s'\n", __func__,
 		       (char *)priv->variant);
 		return -EINVAL;
 	}
 
 	if (priv->variant == H3_EMAC) {
 		if (fdt_getprop(gd->fdt_blob, node,
 				"allwinner,use-internal-phy", NULL))
 			priv->use_internal_phy = true;
 	}
 
 	priv->interface = pdata->phy_interface;
 
 	if (!priv->use_internal_phy)
 		parse_phy_pins(dev);
 
+#ifdef CONFIG_DM_GPIO
+	if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+			    "allwinner,reset-active-low"))
+		reset_flags |= GPIOD_ACTIVE_LOW;
+
+	ret = gpio_request_by_name(dev, "allwinner,reset-gpio", 0,
+				   &priv->reset_gpio, reset_flags);
+
+	if (ret == 0) {
+		ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+					   "allwinner,reset-delays-us", sun8i_pdata->reset_delays, 3);
+	} else if (ret == -ENOENT) {
+		ret = 0;
+	}
+#endif
+
 	return 0;
 }
 
@@ -783,11 +856,11 @@  static const struct udevice_id sun8i_emac_eth_ids[] = {
 U_BOOT_DRIVER(eth_sun8i_emac) = {
 	.name   = "eth_sun8i_emac",
 	.id     = UCLASS_ETH,
 	.of_match = sun8i_emac_eth_ids,
 	.ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
 	.probe  = sun8i_emac_eth_probe,
 	.ops    = &sun8i_emac_eth_ops,
 	.priv_auto_alloc_size = sizeof(struct emac_eth_dev),
-	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+	.platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
 	.flags = DM_FLAG_ALLOC_PRIV_DMA,
 };