diff mbox

[U-Boot,04/11] arm: socfpga: clkmgr: Segregate the Clock Manager for Stratix 10

Message ID 1471878163-3598-5-git-send-email-clsee@altera.com
State Superseded
Delegated to: Marek Vasut
Headers show

Commit Message

Chin Liang See Aug. 22, 2016, 3:02 p.m. UTC 
Segregate the Clock Manager to support both GEN5 SoC and
Stratix 10 SoC.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Ley Foon Tan <lftan@altera.com>
---
 arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Marek Vasut Sept. 5, 2016, 3:58 p.m. UTC | #1 
On 08/22/2016 05:02 PM, Chin Liang See wrote:
> Segregate the Clock Manager to support both GEN5 SoC and
> Stratix 10 SoC.
> 
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Ley Foon Tan <lftan@altera.com>
> ---
>  arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
> index aa71636..0d67b3c 100644
> --- a/arch/arm/mach-socfpga/clock_manager.c
> +++ b/arch/arm/mach-socfpga/clock_manager.c
> @@ -10,6 +10,7 @@
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  static const struct socfpga_clock_manager *clock_manager_base =
>  	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
>  
> @@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)
>  
>  	return clock;
>  }
> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>  
>  unsigned int cm_get_mmc_controller_clk_hz(void)
>  {
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  	uint32_t reg, clock = 0;
>  
>  	/* identify the source of MMC clock */
> @@ -475,8 +478,12 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
>  	/* further divide by 4 as we have fixed divider at wrapper */
>  	clock /= 4;
>  	return clock;
> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> +	return 25000000;
> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>  }
>  
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  unsigned int cm_get_qspi_controller_clk_hz(void)

Are you sure this won't cause build breakage ? I believe this is still
used by the cadence qspi driver.

>  {
>  	uint32_t reg, clock = 0;
> @@ -556,3 +563,4 @@ U_BOOT_CMD(
>  	"display clocks",
>  	""
>  );
> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>
Chin Liang See Sept. 6, 2016, 5:14 a.m. UTC | #2 
On Mon, 2016-09-05 at 17:58 +0200, Marek Vasut wrote:
> On 08/22/2016 05:02 PM, Chin Liang See wrote:
> > Segregate the Clock Manager to support both GEN5 SoC and
> > Stratix 10 SoC.
> > 
> > Signed-off-by: Chin Liang See <clsee@altera.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Ley Foon Tan <lftan@altera.com>
> > ---
> >  arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach
> > -socfpga/clock_manager.c
> > index aa71636..0d67b3c 100644
> > --- a/arch/arm/mach-socfpga/clock_manager.c
> > +++ b/arch/arm/mach-socfpga/clock_manager.c
> > @@ -10,6 +10,7 @@
> >  
> >  DECLARE_GLOBAL_DATA_PTR;
> >  
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  static const struct socfpga_clock_manager *clock_manager_base =
> >  	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> >  
> > @@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> >  
> >  	return clock;
> >  }
> > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> >  
> >  unsigned int cm_get_mmc_controller_clk_hz(void)
> >  {
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  	uint32_t reg, clock = 0;
> >  
> >  	/* identify the source of MMC clock */
> > @@ -475,8 +478,12 @@ unsigned int
> > cm_get_mmc_controller_clk_hz(void)
> >  	/* further divide by 4 as we have fixed divider at wrapper
> > */
> >  	clock /= 4;
> >  	return clock;
> > +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> > +	return 25000000;
> > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> >  }
> >  
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  unsigned int cm_get_qspi_controller_clk_hz(void)
> 
> Are you sure this won't cause build breakage ? I believe this is
> still
> used by the cadence qspi driver.

That is a good question. As for SOC Virtual Platform, we are not
enabling the QSPI controller.

Thanks
Chin Liang

> 
> >  {
> >  	uint32_t reg, clock = 0;
> > @@ -556,3 +563,4 @@ U_BOOT_CMD(
> >  	"display clocks",
> >  	""
> >  );
> > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > 
> 
>
Marek Vasut Sept. 6, 2016, 12:08 p.m. UTC | #3 
On 09/06/2016 07:14 AM, Chin Liang See wrote:
> On Mon, 2016-09-05 at 17:58 +0200, Marek Vasut wrote:
>> On 08/22/2016 05:02 PM, Chin Liang See wrote:
>>> Segregate the Clock Manager to support both GEN5 SoC and
>>> Stratix 10 SoC.
>>>
>>> Signed-off-by: Chin Liang See <clsee@altera.com>
>>> Cc: Marek Vasut <marex@denx.de>
>>> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
>>> Cc: Ley Foon Tan <lftan@altera.com>
>>> ---
>>>  arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++
>>>  1 file changed, 8 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach
>>> -socfpga/clock_manager.c
>>> index aa71636..0d67b3c 100644
>>> --- a/arch/arm/mach-socfpga/clock_manager.c
>>> +++ b/arch/arm/mach-socfpga/clock_manager.c
>>> @@ -10,6 +10,7 @@
>>>  
>>>  DECLARE_GLOBAL_DATA_PTR;
>>>  
>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>  static const struct socfpga_clock_manager *clock_manager_base =
>>>  	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
>>>  
>>> @@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)
>>>  
>>>  	return clock;
>>>  }
>>> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>>>  
>>>  unsigned int cm_get_mmc_controller_clk_hz(void)
>>>  {
>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>  	uint32_t reg, clock = 0;
>>>  
>>>  	/* identify the source of MMC clock */
>>> @@ -475,8 +478,12 @@ unsigned int
>>> cm_get_mmc_controller_clk_hz(void)
>>>  	/* further divide by 4 as we have fixed divider at wrapper
>>> */
>>>  	clock /= 4;
>>>  	return clock;
>>> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
>>> +	return 25000000;
>>> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>>>  }
>>>  
>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>  unsigned int cm_get_qspi_controller_clk_hz(void)
>>
>> Are you sure this won't cause build breakage ? I believe this is
>> still
>> used by the cadence qspi driver.
> 
> That is a good question. As for SOC Virtual Platform, we are not
> enabling the QSPI controller.

When stratix 10 ships, this will be left broken then ?
Chin Liang See Sept. 7, 2016, 1:26 p.m. UTC | #4 
On Tue, 2016-09-06 at 14:08 +0200, Marek Vasut wrote:
> On 09/06/2016 07:14 AM, Chin Liang See wrote:
> > On Mon, 2016-09-05 at 17:58 +0200, Marek Vasut wrote:
> > > On 08/22/2016 05:02 PM, Chin Liang See wrote:
> > > > Segregate the Clock Manager to support both GEN5 SoC and
> > > > Stratix 10 SoC.
> > > > 
> > > > Signed-off-by: Chin Liang See <clsee@altera.com>
> > > > Cc: Marek Vasut <marex@denx.de>
> > > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > > Cc: Ley Foon Tan <lftan@altera.com>
> > > > ---
> > > >  arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++
> > > >  1 file changed, 8 insertions(+)
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/clock_manager.c
> > > > b/arch/arm/mach
> > > > -socfpga/clock_manager.c
> > > > index aa71636..0d67b3c 100644
> > > > --- a/arch/arm/mach-socfpga/clock_manager.c
> > > > +++ b/arch/arm/mach-socfpga/clock_manager.c
> > > > @@ -10,6 +10,7 @@
> > > >  
> > > >  DECLARE_GLOBAL_DATA_PTR;
> > > >  
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > >  static const struct socfpga_clock_manager *clock_manager_base
> > > > =
> > > >  	(struct socfpga_clock_manager
> > > > *)SOCFPGA_CLKMGR_ADDRESS;
> > > >  
> > > > @@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> > > >  
> > > >  	return clock;
> > > >  }
> > > > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > > >  
> > > >  unsigned int cm_get_mmc_controller_clk_hz(void)
> > > >  {
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > >  	uint32_t reg, clock = 0;
> > > >  
> > > >  	/* identify the source of MMC clock */
> > > > @@ -475,8 +478,12 @@ unsigned int
> > > > cm_get_mmc_controller_clk_hz(void)
> > > >  	/* further divide by 4 as we have fixed divider at
> > > > wrapper
> > > > */
> > > >  	clock /= 4;
> > > >  	return clock;
> > > > +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> > > > +	return 25000000;
> > > > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > > >  }
> > > >  
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > >  unsigned int cm_get_qspi_controller_clk_hz(void)
> > > 
> > > Are you sure this won't cause build breakage ? I believe this is
> > > still
> > > used by the cadence qspi driver.
> > 
> > That is a good question. As for SOC Virtual Platform, we are not
> > enabling the QSPI controller.
> 
> When stratix 10 ships, this will be left broken then ?
> 

Definitely not as we will enable and validate this against emulation in
coming weeks.

Thanks
Chin Liang

>
Marek Vasut Sept. 7, 2016, 2:57 p.m. UTC | #5 
On 09/07/2016 03:26 PM, Chin Liang See wrote:
> On Tue, 2016-09-06 at 14:08 +0200, Marek Vasut wrote:
>> On 09/06/2016 07:14 AM, Chin Liang See wrote:
>>> On Mon, 2016-09-05 at 17:58 +0200, Marek Vasut wrote:
>>>> On 08/22/2016 05:02 PM, Chin Liang See wrote:
>>>>> Segregate the Clock Manager to support both GEN5 SoC and
>>>>> Stratix 10 SoC.
>>>>>
>>>>> Signed-off-by: Chin Liang See <clsee@altera.com>
>>>>> Cc: Marek Vasut <marex@denx.de>
>>>>> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
>>>>> Cc: Ley Foon Tan <lftan@altera.com>
>>>>> ---
>>>>>  arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++
>>>>>  1 file changed, 8 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/mach-socfpga/clock_manager.c
>>>>> b/arch/arm/mach
>>>>> -socfpga/clock_manager.c
>>>>> index aa71636..0d67b3c 100644
>>>>> --- a/arch/arm/mach-socfpga/clock_manager.c
>>>>> +++ b/arch/arm/mach-socfpga/clock_manager.c
>>>>> @@ -10,6 +10,7 @@
>>>>>  
>>>>>  DECLARE_GLOBAL_DATA_PTR;
>>>>>  
>>>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>>>  static const struct socfpga_clock_manager *clock_manager_base
>>>>> =
>>>>>  	(struct socfpga_clock_manager
>>>>> *)SOCFPGA_CLKMGR_ADDRESS;
>>>>>  
>>>>> @@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)
>>>>>  
>>>>>  	return clock;
>>>>>  }
>>>>> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>>>>>  
>>>>>  unsigned int cm_get_mmc_controller_clk_hz(void)
>>>>>  {
>>>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>>>  	uint32_t reg, clock = 0;
>>>>>  
>>>>>  	/* identify the source of MMC clock */
>>>>> @@ -475,8 +478,12 @@ unsigned int
>>>>> cm_get_mmc_controller_clk_hz(void)
>>>>>  	/* further divide by 4 as we have fixed divider at
>>>>> wrapper
>>>>> */
>>>>>  	clock /= 4;
>>>>>  	return clock;
>>>>> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
>>>>> +	return 25000000;
>>>>> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>>>>>  }
>>>>>  
>>>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>>>  unsigned int cm_get_qspi_controller_clk_hz(void)
>>>>
>>>> Are you sure this won't cause build breakage ? I believe this is
>>>> still
>>>> used by the cadence qspi driver.
>>>
>>> That is a good question. As for SOC Virtual Platform, we are not
>>> enabling the QSPI controller.
>>
>> When stratix 10 ships, this will be left broken then ?
>>
> 
> Definitely not as we will enable and validate this against emulation in
> coming weeks.

Great, thanks. U-Boot 2016.09 is out on sept. 12 , so that should give
you some space to clean this up.
diff mbox

Patch

diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index aa71636..0d67b3c 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -10,6 +10,7 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static const struct socfpga_clock_manager *clock_manager_base =
 	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
@@ -446,9 +447,11 @@  unsigned int cm_get_l4_sp_clk_hz(void)
 
 	return clock;
 }
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
 
 unsigned int cm_get_mmc_controller_clk_hz(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 	uint32_t reg, clock = 0;
 
 	/* identify the source of MMC clock */
@@ -475,8 +478,12 @@  unsigned int cm_get_mmc_controller_clk_hz(void)
 	/* further divide by 4 as we have fixed divider at wrapper */
 	clock /= 4;
 	return clock;
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+	return 25000000;
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
 }
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 unsigned int cm_get_qspi_controller_clk_hz(void)
 {
 	uint32_t reg, clock = 0;
@@ -556,3 +563,4 @@  U_BOOT_CMD(
 	"display clocks",
 	""
 );
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */