diff mbox

[U-Boot,V2,1/3] freescale/qixis: Add support for booting from SD/QSPI

Message ID 1451557744-12838-2-git-send-email-Qianyu.Gong@nxp.com
State Accepted
Commit 98d9aa4013d9ad4df199297e79d955f55bd6eead
Delegated to: York Sun
Headers show

Commit Message

Gong Qianyu Dec. 31, 2015, 10:29 a.m. UTC 
From: Gong Qianyu <Qianyu.Gong@freescale.com>

1.Use "qixis_reset sd" to boot from SD
2.Use "qixis_reset sd_qspi" to boot from SD with QSPI support
3.Use "qixis_reset qspi" to boot from QSPI flash

On some SoCs such as LS1021A and LS1043A, IFC and QSPI could be
pin-multiplexed. So the switches are different between SD boot with
IFC support and SD boot with QSPI support. The default booting from
SD is with IFC support.

Once QSPI is enabled(IFC disabled), only use I2C to access QIXIS.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
---
V2:
 - Use qixis_write_i2c instead of QIXIS_WRITE once QSPI is enabled.

 board/freescale/common/qixis.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

Comments

York Sun Jan. 27, 2016, 4:42 p.m. UTC | #1 
On 12/31/2015 02:37 AM, Gong Qianyu wrote:
> From: Gong Qianyu <Qianyu.Gong@freescale.com>
> 
> 1.Use "qixis_reset sd" to boot from SD
> 2.Use "qixis_reset sd_qspi" to boot from SD with QSPI support
> 3.Use "qixis_reset qspi" to boot from QSPI flash
> 
> On some SoCs such as LS1021A and LS1043A, IFC and QSPI could be
> pin-multiplexed. So the switches are different between SD boot with
> IFC support and SD boot with QSPI support. The default booting from
> SD is with IFC support.
> 
> Once QSPI is enabled(IFC disabled), only use I2C to access QIXIS.
> 
> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
> ---
> V2:
>  - Use qixis_write_i2c instead of QIXIS_WRITE once QSPI is enabled.
> 
>  board/freescale/common/qixis.c | 36 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)

Applied to u-boot-fsl-qoriq master. Awaiting upstream.

Thanks.

York
diff mbox

Patch

diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 9f6b0e7..113295f 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -216,6 +216,39 @@  int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #else
 		printf("Not implemented\n");
 #endif
+	} else if (strcmp(argv[1], "sd") == 0) {
+#ifdef QIXIS_LBMAP_SD
+		QIXIS_WRITE(rst_ctl, 0x30);
+		QIXIS_WRITE(rcfg_ctl, 0);
+		set_lbmap(QIXIS_LBMAP_SD);
+		set_rcw_src(QIXIS_RCW_SRC_SD);
+		QIXIS_WRITE(rcfg_ctl, 0x20);
+		QIXIS_WRITE(rcfg_ctl, 0x21);
+#else
+		printf("Not implemented\n");
+#endif
+	} else if (strcmp(argv[1], "sd_qspi") == 0) {
+#ifdef QIXIS_LBMAP_SD_QSPI
+		QIXIS_WRITE(rst_ctl, 0x30);
+		QIXIS_WRITE(rcfg_ctl, 0);
+		set_lbmap(QIXIS_LBMAP_SD_QSPI);
+		set_rcw_src(QIXIS_RCW_SRC_SD);
+		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
+		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+#else
+		printf("Not implemented\n");
+#endif
+	} else if (strcmp(argv[1], "qspi") == 0) {
+#ifdef QIXIS_LBMAP_QSPI
+		QIXIS_WRITE(rst_ctl, 0x30);
+		QIXIS_WRITE(rcfg_ctl, 0);
+		set_lbmap(QIXIS_LBMAP_QSPI);
+		set_rcw_src(QIXIS_RCW_SRC_QSPI);
+		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
+		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+#else
+		printf("Not implemented\n");
+#endif
 	} else if (strcmp(argv[1], "watchdog") == 0) {
 		static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
 					  "1min", "2min", "4min", "8min"};
@@ -255,6 +288,9 @@  U_BOOT_CMD(
 	"- hard reset to default bank\n"
 	"qixis_reset altbank - reset to alternate bank\n"
 	"qixis_reset nand - reset to nand\n"
+	"qixis_reset sd - reset to sd\n"
+	"qixis_reset sd_qspi - reset to sd with qspi support\n"
+	"qixis_reset qspi - reset to qspi\n"
 	"qixis watchdog <watchdog_period> - set the watchdog period\n"
 	"	period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
 	"qixis_reset dump - display the QIXIS registers\n"