diff mbox

[U-Boot] serial_mxc: Fix setup of UARTx_UFCR register

Message ID 1448456880-20140-1-git-send-email-maximilian.schwerin@tigris.de
State Awaiting Upstream
Delegated to: Stefano Babic
Headers show

Commit Message

Maximilian Schwerin Nov. 25, 2015, 1:08 p.m. UTC 
This patch writes the default values for TXTL and RXTL to UARTx_UFCR.
Without this patch some older kernel versions crash as UARTx_UFCR was
not always correctly initialized.

Signed-off-by: Maximilian Schwerin <maximilian.schwerin@tigris.de>
---
 drivers/serial/serial_mxc.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

Comments

Stefano Babic Jan. 3, 2016, 2:23 p.m. UTC | #1 
On 25/11/2015 14:08, Maximilian Schwerin wrote:
> This patch writes the default values for TXTL and RXTL to UARTx_UFCR.
> Without this patch some older kernel versions crash as UARTx_UFCR was
> not always correctly initialized.
> 
> Signed-off-by: Maximilian Schwerin <maximilian.schwerin@tigris.de>
> ---


Applied to u-boot-imx, thanks!

Best regards,
Stefano Babic
diff mbox

Patch

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index d6cf1d8..51485c0 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -75,6 +75,7 @@ 
 #define  UCR4_DREN	 (1<<0)  /* Recv data ready interrupt enable */
 #define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 #define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
+#define  UFCR_RFDIV_SHF  7      /* Reference freq divider shift */
 #define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 #define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 #define  USR1_RTSS	 (1<<14) /* RTS pin status */
@@ -135,6 +136,10 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define TXTL  2 /* reset default */
+#define RXTL  1 /* reset default */
+#define RFDIV 4 /* divide input clock by 2 */
+
 static void mxc_serial_setbrg(void)
 {
 	u32 clk = imx_get_uartclk();
@@ -142,7 +147,9 @@  static void mxc_serial_setbrg(void)
 	if (!gd->baudrate)
 		gd->baudrate = CONFIG_BAUDRATE;
 
-	__REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
+	__REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF)
+		| (TXTL << UFCR_TXTL_SHF)
+		| (RXTL << UFCR_RXTL_SHF);
 	__REG(UART_PHYS + UBIR) = 0xf;
 	__REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);