| Message ID | 1441348268-18547-1-git-send-email-sivadur@xilinx.com |
|---|---|
| State | Superseded |
| Delegated to: | Michal Simek |
| Headers | show |
On Friday, September 04, 2015 at 08:31:07 AM, Siva Durga Prasad Paladugu wrote: > Added USB XHCI driver support for zynqmp. > > Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Hi, looks like in the meantime, some xhci implementations switches to OF (see for example xhci-exynos5.c), which I believe is also already used on Zynq. Maybe you should consider that as well, given that this patch is scheduled after 2015.10 release anyway. > +struct zynqmp_xhci { > + struct xhci_hccr *hcd; > + struct dwc3 *dwc3_reg; > +}; > + > +static struct zynqmp_xhci zynqmp_xhci; > > +unsigned long ctr_addr[] = CONFIG_ZYNQMP_XHCI_LIST; > + > +__weak int __board_usb_init(int index, enum usb_init_type init) Please, no functions starting with underscores. > +{ > + return 0; This function is not used, remove it? > +} > + > +void usb_phy_reset(struct dwc3 *dwc3_reg) > +{ > + /* Assert USB3 PHY reset */ > + setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); > + > + /* Assert USB2 PHY reset */ > + setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); > + > + udelay(10); > + > + /* Clear USB3 PHY reset */ > + clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); > + > + /* Clear USB2 PHY reset */ > + clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); > +} [...] Best regards, Marek Vasut
Hi, On 4 September 2015 at 00:31, Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> wrote: > Added USB XHCI driver support for zynqmp. > > Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> > --- > Changes for v4: > - Added sanity check for index as per > review comment > Changes for v3: > - Decreased the phy reset delay to 10 micro secs > - Defined base addresses in board config file as > per review comment. > Changes for v2: > - Moved all from xhci-zynqmp.h to .c file as > per review comment > - Removed ad-hoc function zynqmp_xhci_core_exit() > as per review comment > --- > drivers/usb/host/Makefile | 1 + > drivers/usb/host/xhci-zynqmp.c | 148 ++++++++++++++++++++++++++++++++++++ > include/configs/xilinx_zynqmp_ep.h | 2 + > 3 files changed, 151 insertions(+), 0 deletions(-) > create mode 100644 drivers/usb/host/xhci-zynqmp.c Can you convert this to use driver model? See xhci-exynos5.c for an example. Regards, Simon
On Saturday, September 05, 2015 at 03:47:12 PM, Simon Glass wrote: > Hi, > > On 4 September 2015 at 00:31, Siva Durga Prasad Paladugu > > <siva.durga.paladugu@xilinx.com> wrote: > > Added USB XHCI driver support for zynqmp. > > > > Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> > > --- > > Changes for v4: > > - Added sanity check for index as per > > > > review comment > > > > Changes for v3: > > - Decreased the phy reset delay to 10 micro secs > > - Defined base addresses in board config file as > > > > per review comment. > > > > Changes for v2: > > - Moved all from xhci-zynqmp.h to .c file as > > > > per review comment > > > > - Removed ad-hoc function zynqmp_xhci_core_exit() > > > > as per review comment > > > > --- > > > > drivers/usb/host/Makefile | 1 + > > drivers/usb/host/xhci-zynqmp.c | 148 > > ++++++++++++++++++++++++++++++++++++ include/configs/xilinx_zynqmp_ep.h > > | 2 + > > 3 files changed, 151 insertions(+), 0 deletions(-) > > create mode 100644 drivers/usb/host/xhci-zynqmp.c > > Can you convert this to use driver model? See xhci-exynos5.c for an > example. Right :) Best regards, Marek Vasut
Hi Marek, > -----Original Message----- > From: Marek Vasut [mailto:marex@denx.de] > Sent: Saturday, September 05, 2015 6:46 PM > To: Siva Durga Prasad Paladugu > Cc: u-boot@lists.denx.de; Siva Durga Prasad Paladugu > Subject: Re: [PATCH v4 1/2] usb: zynqmp: Add XHCI driver support > > On Friday, September 04, 2015 at 08:31:07 AM, Siva Durga Prasad Paladugu > wrote: > > Added USB XHCI driver support for zynqmp. > > > > Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> > > Hi, > > looks like in the meantime, some xhci implementations switches to OF (see > for example xhci-exynos5.c), which I believe is also already used on Zynq. > Maybe you should consider that as well, given that this patch is scheduled > after 2015.10 release anyway. This patch is for ZynqMP not for Zynq. ZynqMP, we haven't yet moved to OF. Regards, Siva > > > +struct zynqmp_xhci { > > + struct xhci_hccr *hcd; > > + struct dwc3 *dwc3_reg; > > +}; > > + > > +static struct zynqmp_xhci zynqmp_xhci; > > > > +unsigned long ctr_addr[] = CONFIG_ZYNQMP_XHCI_LIST; > > + > > +__weak int __board_usb_init(int index, enum usb_init_type init) > > Please, no functions starting with underscores. > > > +{ > > + return 0; > > This function is not used, remove it? > > > +} > > + > > +void usb_phy_reset(struct dwc3 *dwc3_reg) { > > + /* Assert USB3 PHY reset */ > > + setbits_le32(&dwc3_reg->g_usb3pipectl[0], > > +DWC3_GUSB3PIPECTL_PHYSOFTRST); > > + > > + /* Assert USB2 PHY reset */ > > + setbits_le32(&dwc3_reg->g_usb2phycfg, > DWC3_GUSB2PHYCFG_PHYSOFTRST); > > + > > + udelay(10); > > + > > + /* Clear USB3 PHY reset */ > > + clrbits_le32(&dwc3_reg->g_usb3pipectl[0], > > +DWC3_GUSB3PIPECTL_PHYSOFTRST); > > + > > + /* Clear USB2 PHY reset */ > > + clrbits_le32(&dwc3_reg->g_usb2phycfg, > DWC3_GUSB2PHYCFG_PHYSOFTRST); > > +} > [...] > Best regards, > Marek Vasut
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index f70f38c..645b990 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o +obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o diff --git a/drivers/usb/host/xhci-zynqmp.c b/drivers/usb/host/xhci-zynqmp.c new file mode 100644 index 0000000..7c4a413 --- /dev/null +++ b/drivers/usb/host/xhci-zynqmp.c @@ -0,0 +1,148 @@ +/* + * Copyright 2015 Xilinx, Inc. + * + * Zynq USB HOST xHCI Controller + * + * Author: Siva Durga Prasad Paladugu<sivadur@xilinx.com> + * + * This file was reused from Freescale USB xHCI + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <usb.h> +#include <asm-generic/errno.h> +#include <asm/arch-zynqmp/hardware.h> +#include <linux/compat.h> +#include <linux/usb/dwc3.h> +#include "xhci.h" + +/* Declare global data pointer */ +DECLARE_GLOBAL_DATA_PTR; + +/* Default to the ZYNQMP XHCI defines */ +#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 +#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC +#define USB3_PHY_PARTIAL_RX_POWERON BIT(6) +#define USB3_PHY_RX_POWERON BIT(14) +#define USB3_PHY_TX_POWERON BIT(15) +#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) +#define USB3_PWRCTL_CLK_CMD_SHIFT 14 +#define USB3_PWRCTL_CLK_FREQ_SHIFT 22 + +/* USBOTGSS_WRAPPER definitions */ +#define USBOTGSS_WRAPRESET BIT(17) +#define USBOTGSS_DMADISABLE BIT(16) +#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) +#define USBOTGSS_STANDBYMODE_SMRT BIT(5) +#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) +#define USBOTGSS_IDLEMODE_NOIDLE BIT(2) +#define USBOTGSS_IDLEMODE_SMRT BIT(3) +#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) + +/* USBOTGSS_IRQENABLE_SET_0 bit */ +#define USBOTGSS_COREIRQ_EN BIT(1) + +/* USBOTGSS_IRQENABLE_SET_1 bits */ +#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) +#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) +#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) +#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) + +struct zynqmp_xhci { + struct xhci_hccr *hcd; + struct dwc3 *dwc3_reg; +}; + +static struct zynqmp_xhci zynqmp_xhci; + +unsigned long ctr_addr[] = CONFIG_ZYNQMP_XHCI_LIST; + +__weak int __board_usb_init(int index, enum usb_init_type init) +{ + return 0; +} + +void usb_phy_reset(struct dwc3 *dwc3_reg) +{ + /* Assert USB3 PHY reset */ + setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); + + /* Assert USB2 PHY reset */ + setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); + + udelay(10); + + /* Clear USB3 PHY reset */ + clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); + + /* Clear USB2 PHY reset */ + clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); +} + +static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci) +{ + int ret = 0; + + ret = dwc3_core_init(zynqmp_xhci->dwc3_reg); + if (ret) { + debug("%s:failed to initialize core\n", __func__); + return ret; + } + + /* We are hard-coding DWC3 core to Host Mode */ + dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); + + return ret; +} + +int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) +{ + struct zynqmp_xhci *ctx = &zynqmp_xhci; + int ret = 0; + + if (index < 0 || index >= ARRAY_SIZE(ctr_addr)) + return -EINVAL; + + ctx->hcd = (struct xhci_hccr *)ctr_addr[index]; + ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); + + ret = board_usb_init(index, USB_INIT_HOST); + if (ret != 0) { + puts("Failed to initialize board for USB\n"); + return ret; + } + + ret = zynqmp_xhci_core_init(ctx); + if (ret < 0) { + puts("Failed to initialize xhci\n"); + return ret; + } + + *hccr = (struct xhci_hccr *)ctx->hcd; + *hcor = (struct xhci_hcor *)((uint32_t) *hccr + + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); + + debug("zynqmp-xhci: init hccr %x and hcor %x hc_length %d\n", + (uint32_t)*hccr, (uint32_t)*hcor, + (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); + + return ret; +} + +void xhci_hcd_stop(int index) +{ + /* + * Currently zynqmp socs do not support PHY shutdown from + * sw. But this support may be added in future socs. + */ + + return 0; +} diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index e476eb1..abb3c40 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -24,6 +24,8 @@ #define CONFIG_SYS_I2C_ZYNQ #define CONFIG_ZYNQ_EEPROM #define CONFIG_AHCI +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ + ZYNQMP_USB1_XHCI_BASEADDR} #include <configs/xilinx_zynqmp.h>
Added USB XHCI driver support for zynqmp. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> --- Changes for v4: - Added sanity check for index as per review comment Changes for v3: - Decreased the phy reset delay to 10 micro secs - Defined base addresses in board config file as per review comment. Changes for v2: - Moved all from xhci-zynqmp.h to .c file as per review comment - Removed ad-hoc function zynqmp_xhci_core_exit() as per review comment --- drivers/usb/host/Makefile | 1 + drivers/usb/host/xhci-zynqmp.c | 148 ++++++++++++++++++++++++++++++++++++ include/configs/xilinx_zynqmp_ep.h | 2 + 3 files changed, 151 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/xhci-zynqmp.c