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[U-Boot,3/8] imx: mx6: L2cache: Enable the double line fill for i.MX6DQP

Message ID 1433923603-28119-3-git-send-email-Peng.Fan@freescale.com
State Changes Requested
Headers show

Commit Message

Peng Fan June 10, 2015, 8:06 a.m. UTC 
From: "Ye.Li" <B37916@freescale.com>

Since i.MX6DQP has fixed the L2 cache issue, enable the double line
fill feature to provide better performance.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
---
 arch/arm/cpu/armv7/mx6/soc.c | 3 +++
 1 file changed, 3 insertions(+)
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Patch

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 29de624..e3474e7 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -645,6 +645,9 @@  void v7_outer_cache_enable(void)
 
 #ifndef CONFIG_MX6Q
 	val |= 0x40800000;
+#else
+	if (is_mx6dqp())
+		val |= 0x40800000;
 #endif
 	writel(val, &pl310->pl310_prefetch_ctrl);