| Message ID | 1433392730-4269-1-git-send-email-lokeshvutla@ti.com |
|---|---|
| State | Accepted |
| Delegated to: | Tom Rini |
| Headers | show |
On Thu, Jun 04, 2015 at 10:08:50AM +0530, Lokesh Vutla wrote: > Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after > warm reset, emif needs to be configured to bring it back to a known > state. So configure EMIF during warm reset. > > Reported-by: Roger Quadros <rogerq@ti.com> > Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Applied to u-boot/master, thanks!
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index ca22c00..f5b22f6 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1170,7 +1170,7 @@ static void do_sdram_init(u32 base) * Changing the timing registers in EMIF can happen(going from one * OPP to another) */ - if (!(in_sdram || warm_reset())) { + if (!in_sdram && (!warm_reset() || is_dra7xx())) { if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_LPDDR2) lpddr2_init(base, regs); @@ -1178,7 +1178,7 @@ static void do_sdram_init(u32 base) ddr3_init(base, regs); } if (warm_reset() && (emif_sdram_type(regs->sdram_config) == - EMIF_SDRAM_TYPE_DDR3)) { + EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) { set_lpmode_selfrefresh(base); emif_reset_phy(base); omap5_ddr3_leveling(base, regs);
Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after warm reset, emif needs to be configured to bring it back to a known state. So configure EMIF during warm reset. Reported-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> --- arch/arm/cpu/armv7/omap-common/emif-common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)