| Message ID | 1424122683-29357-2-git-send-email-otavio@ossystems.com.br |
|---|---|
| State | Changes Requested |
| Headers | show |
On 2/16/2015 2:38 PM, Otavio Salvador wrote: > Some boards cannot do voltage negotiation but need to set the VSELECT > bit forcely to ensure it to work at 1.8V. > > This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use. > > Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> > --- > > doc/README.fsl-esdhc | 1 + > drivers/mmc/fsl_esdhc.c | 4 ++++ > 2 files changed, 5 insertions(+) > > diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc > index b70f271..619c6b2 100644 > --- a/doc/README.fsl-esdhc > +++ b/doc/README.fsl-esdhc > @@ -1,5 +1,6 @@ > CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode. > CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode. > +CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V. > > Accessing ESDHC registers can be determined by ESDHC IP's endian > mode or processor's endian mode. > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c > index eb0fbf9..5fde2b6 100644 > --- a/drivers/mmc/fsl_esdhc.c > +++ b/drivers/mmc/fsl_esdhc.c > @@ -524,6 +524,10 @@ static int esdhc_init(struct mmc *mmc) > /* Set timout to the maximum value */ > esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); > > +#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT > + esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); > +#endif > + > return 0; > } > > What if 1 controller needs it set and another needs it clear?
On Tuesday, February 17, 2015 at 02:38:31 AM, Troy Kisky wrote: > On 2/16/2015 2:38 PM, Otavio Salvador wrote: > > Some boards cannot do voltage negotiation but need to set the VSELECT > > bit forcely to ensure it to work at 1.8V. > > > > This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use. > > > > Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> > > --- > > > > doc/README.fsl-esdhc | 1 + > > drivers/mmc/fsl_esdhc.c | 4 ++++ > > 2 files changed, 5 insertions(+) > > > > diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc > > index b70f271..619c6b2 100644 > > --- a/doc/README.fsl-esdhc > > +++ b/doc/README.fsl-esdhc > > @@ -1,5 +1,6 @@ > > > > CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode. > > CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode. > > > > +CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V. > > > > Accessing ESDHC registers can be determined by ESDHC IP's endian > > mode or processor's endian mode. > > > > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c > > index eb0fbf9..5fde2b6 100644 > > --- a/drivers/mmc/fsl_esdhc.c > > +++ b/drivers/mmc/fsl_esdhc.c > > @@ -524,6 +524,10 @@ static int esdhc_init(struct mmc *mmc) > > > > /* Set timout to the maximum value */ > > esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); > > > > +#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT > > + esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); > > +#endif > > + > > > > return 0; > > > > } > > What if 1 controller needs it set and another needs it clear? Then this code won't work, duh ;-) Best regards, Marek Vasut
On Mon, Feb 16, 2015 at 11:38 PM, Troy Kisky <troy.kisky@boundarydevices.com> wrote: > On 2/16/2015 2:38 PM, Otavio Salvador wrote: >> Some boards cannot do voltage negotiation but need to set the VSELECT >> bit forcely to ensure it to work at 1.8V. >> >> This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use. >> >> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> ... > > What if 1 controller needs it set and another needs it clear? I am not sure it makes much sense to have one in 3V3 and another 1V8. Does it?
On 2/17/2015 5:36 AM, Otavio Salvador wrote: > On Mon, Feb 16, 2015 at 11:38 PM, Troy Kisky > <troy.kisky@boundarydevices.com> wrote: >> On 2/16/2015 2:38 PM, Otavio Salvador wrote: >>> Some boards cannot do voltage negotiation but need to set the VSELECT >>> bit forcely to ensure it to work at 1.8V. >>> >>> This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use. >>> >>> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> > ... >> >> What if 1 controller needs it set and another needs it clear? > > I am not sure it makes much sense to have one in 3V3 and another 1V8. Does it? > I guess if the need ever arises it can be changed then. It just seems better to pass this as a flag for the controller now.
On Tuesday, February 17, 2015 at 06:18:31 PM, Troy Kisky wrote: > On 2/17/2015 5:36 AM, Otavio Salvador wrote: > > On Mon, Feb 16, 2015 at 11:38 PM, Troy Kisky > > > > <troy.kisky@boundarydevices.com> wrote: > >> On 2/16/2015 2:38 PM, Otavio Salvador wrote: > >>> Some boards cannot do voltage negotiation but need to set the VSELECT > >>> bit forcely to ensure it to work at 1.8V. > >>> > >>> This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use. > >>> > >>> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> > > > > ... > > > >> What if 1 controller needs it set and another needs it clear? > > > > I am not sure it makes much sense to have one in 3V3 and another 1V8. > > Does it? > > I guess if the need ever arises it can be changed then. It just seems > better to pass this as a flag for the controller now. Or even make it configurable via DT . Best regards, Marek Vasut
On Tue, Feb 17, 2015 at 5:43 PM, Marek Vasut <marex@denx.de> wrote: > On Tuesday, February 17, 2015 at 06:18:31 PM, Troy Kisky wrote: >> On 2/17/2015 5:36 AM, Otavio Salvador wrote: >> > On Mon, Feb 16, 2015 at 11:38 PM, Troy Kisky >> > >> > <troy.kisky@boundarydevices.com> wrote: >> >> On 2/16/2015 2:38 PM, Otavio Salvador wrote: >> >>> Some boards cannot do voltage negotiation but need to set the VSELECT >> >>> bit forcely to ensure it to work at 1.8V. >> >>> >> >>> This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use. >> >>> >> >>> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> >> > >> > ... >> > >> >> What if 1 controller needs it set and another needs it clear? >> > >> > I am not sure it makes much sense to have one in 3V3 and another 1V8. >> > Does it? >> >> I guess if the need ever arises it can be changed then. It just seems >> better to pass this as a flag for the controller now. > > Or even make it configurable via DT . Could this be changed later?
diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc index b70f271..619c6b2 100644 --- a/doc/README.fsl-esdhc +++ b/doc/README.fsl-esdhc @@ -1,5 +1,6 @@ CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode. CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode. +CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V. Accessing ESDHC registers can be determined by ESDHC IP's endian mode or processor's endian mode. diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index eb0fbf9..5fde2b6 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -524,6 +524,10 @@ static int esdhc_init(struct mmc *mmc) /* Set timout to the maximum value */ esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); +#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT + esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); +#endif + return 0; }
Some boards cannot do voltage negotiation but need to set the VSELECT bit forcely to ensure it to work at 1.8V. This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> --- doc/README.fsl-esdhc | 1 + drivers/mmc/fsl_esdhc.c | 4 ++++ 2 files changed, 5 insertions(+)