[U-Boot] mx53loco: Fix boot hang during reboot stress test

From: Fabio Estevam <fabio.estevam@freescale.com>

Currently by running the following test:

=> setenv bootcmd reset
=> save
=> reset

, we observe a hang after approximately 20-30 minutes of stress reboot test.

Investigation of this issue revealed that when a single DDR chip select is used,
the hang does not happen. It only happens when the two chip selects are active.

MX53 reference manual states at "28.6.2 Memory ZQ calibration sequence":

"The controller must keep the memory lines quiet (except for CK) for the ZQ
calibration time as defined in the Jedec (512 cycles for ZQCL after reset, 256
for other ZQCL and 64 for ZQCS)."

According to the SDE_0 and SDE_1 bit descriptions from register ESDCTL_ESDCTL:

"Writing 1 to SDE0 or SDE1 will initiate power up delays as JEDEC defines.
Power up delays are a function of the configured memory type (DDR2/DDR3/LPDDR2)"

So make sure to activate one chip select at time (CS0 first and then CS1 later),
so that the required JEDEC delay is respected for each chip select.

With this change applied the board has gone through three days of reboot stress
test without any hang.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 board/freescale/mx53loco/imximage.cfg | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Hi Fabio,

On 09/02/2015 10:29, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
> 
> Currently by running the following test:
> 
> => setenv bootcmd reset
> => save
> => reset
> 
> , we observe a hang after approximately 20-30 minutes of stress reboot test.
> 
> Investigation of this issue revealed that when a single DDR chip select is used,
> the hang does not happen. It only happens when the two chip selects are active.
> 
> MX53 reference manual states at "28.6.2 Memory ZQ calibration sequence":
> 
> "The controller must keep the memory lines quiet (except for CK) for the ZQ
> calibration time as defined in the Jedec (512 cycles for ZQCL after reset, 256
> for other ZQCL and 64 for ZQCS)."
> 
> According to the SDE_0 and SDE_1 bit descriptions from register ESDCTL_ESDCTL:
> 
> "Writing 1 to SDE0 or SDE1 will initiate power up delays as JEDEC defines.
> Power up delays are a function of the configured memory type (DDR2/DDR3/LPDDR2)"
> 
> So make sure to activate one chip select at time (CS0 first and then CS1 later),
> so that the required JEDEC delay is respected for each chip select.
> 
> With this change applied the board has gone through three days of reboot stress
> test without any hang.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
>  board/freescale/mx53loco/imximage.cfg | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg
> index d1c1931..a5f1d98 100644
> --- a/board/freescale/mx53loco/imximage.cfg
> +++ b/board/freescale/mx53loco/imximage.cfg
> @@ -59,7 +59,7 @@ DATA 4 0x63fd9090 0x4d444c44
>  DATA 4 0x63fd907c 0x01370138
>  DATA 4 0x63fd9080 0x013b013c
>  DATA 4 0x63fd9018 0x00011740
> -DATA 4 0x63fd9000 0xc3190000
> +DATA 4 0x63fd9000 0x83190000
>  DATA 4 0x63fd900c 0x9f5152e3
>  DATA 4 0x63fd9010 0xb68e8a63
>  DATA 4 0x63fd9014 0x01ff00db
> @@ -72,6 +72,7 @@ DATA 4 0x63fd901c 0x00008033
>  DATA 4 0x63fd901c 0x00028031
>  DATA 4 0x63fd901c 0x052080b0
>  DATA 4 0x63fd901c 0x04008040
> +DATA 4 0x63fd9000 0xc3190000
>  DATA 4 0x63fd901c 0x0000803a
>  DATA 4 0x63fd901c 0x0000803b
>  DATA 4 0x63fd901c 0x00028039
> 

Good catch !

Acked-by: Stefano Babic <sbabic@denx.de>

Best regards,
Stefano Babic