diff mbox

[U-Boot,PATCHv4,1/6] ARM: HYP/non-sec: add the pen address BE mode support.

Message ID 1416562859-37857-2-git-send-email-Li.Xiubo@freescale.com
State Accepted
Delegated to: York Sun
Headers show

Commit Message

Xiubo Li Nov. 21, 2014, 9:40 a.m. UTC 
For some SoCs, the pen address register maybe in BE mode and the
CPUs are in LE mode.

This patch adds BE mode support for smp pen address.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
---
 arch/arm/cpu/armv7/nonsec_virt.S | 3 +++
 1 file changed, 3 insertions(+)

Comments

York Sun Dec. 11, 2014, 7:08 p.m. UTC | #1 
On 11/21/2014 01:40 AM, Xiubo Li wrote:
> For some SoCs, the pen address register maybe in BE mode and the
> CPUs are in LE mode.
> 
> This patch adds BE mode support for smp pen address.
> 
> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> Acked-by: York Sun <yorksun@freescale.com>
> ---

Applied to u-boot-fsl-qoriq master, awaiting upstream.

York
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 745670e..1ab5d54 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -191,6 +191,9 @@  ENTRY(smp_waitloop)
 	wfi
 	ldr	r1, =CONFIG_SMP_PEN_ADDR	@ load start address
 	ldr	r1, [r1]
+#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
+	rev	r1, r1
+#endif
 	cmp	r0, r1			@ make sure we dont execute this code
 	beq	smp_waitloop		@ again (due to a spurious wakeup)
 	mov	r0, r1