| Message ID | 1411706256-33037-2-git-send-email-B45475@freescale.com |
|---|---|
| State | Rejected |
| Delegated to: | York Sun |
| Headers | show |
On 9/25/14 9:37 PM, "Zhao Qiang" <B45475@freescale.com> wrote: >T2080 v1.0 has this errata while v1.1 has fixed >this errata by hardware, add a new function to >check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first, >if the cpu is T2080 and version is not v1.0, doesn't >run the a007212 errata_workaround. > >Signed-off-by: Zhao Qiang <B45475@freescale.com> >--- Qiang, I don't agree with your analysis. This workaround has two parts. One part is to to disable DDR PLL in RCW. The second part is to detect DDR PLL is disabled and to implement the software workaround to bring DDR up. U-boot has the second part, it is safe to apply to all versions for affected SoC. I put in the comments. Your patch detects the SVR and decide if the workaround should be applied. This is wrong. It should detect if DDR PLL is disabled. In case an old RCW is used, you don't want to end up with a dead board because DDR is disabled. York
On 9/26/14 1:01 PM, York Sun wrote: > -----Original Message----- > From: Sun York-R58495 > Sent: Friday, September 26, 2014 1:01 PM > To: Zhao Qiang-B45475; u-boot@lists.denx.de > Cc: Xie Xiaobo-R63061; Zhao Qiang-B45475 > Subject: Re: [PATCH 2/2] powerpc/mpc85xx: modify erratum A007212 > > On 9/25/14 9:37 PM, "Zhao Qiang" <B45475@freescale.com> wrote: > > >T2080 v1.0 has this errata while v1.1 has fixed this errata by > >hardware, add a new function to check the SVR_SOC_VER, SVR_MAJ and > >SVR_MIN first, if the cpu is T2080 and version is not v1.0, doesn't run > >the a007212 errata_workaround. > > > >Signed-off-by: Zhao Qiang <B45475@freescale.com> > >--- > > > Qiang, > > I don't agree with your analysis. > > This workaround has two parts. One part is to to disable DDR PLL in RCW. > The second part is to detect DDR PLL is disabled and to implement the > software workaround to bring DDR up. U-boot has the second part, it is > safe to apply to all versions for affected SoC. I put in the comments. > Your patch detects the SVR and decide if the workaround should be applied. > This is wrong. It should detect if DDR PLL is disabled. In case an old > RCW is used, you don't want to end up with a dead board because DDR is > disabled. OK , got it , I will modify it for v2. Thanks for you comment. > > York Best Regards Zhao Qiang
On 09/25/2014 10:55 PM, Zhao Qiang-B45475 wrote: > > On 9/26/14 1:01 PM, York Sun wrote: > >> -----Original Message----- >> From: Sun York-R58495 >> Sent: Friday, September 26, 2014 1:01 PM >> To: Zhao Qiang-B45475; u-boot@lists.denx.de >> Cc: Xie Xiaobo-R63061; Zhao Qiang-B45475 >> Subject: Re: [PATCH 2/2] powerpc/mpc85xx: modify erratum A007212 >> >> On 9/25/14 9:37 PM, "Zhao Qiang" <B45475@freescale.com> wrote: >> >>> T2080 v1.0 has this errata while v1.1 has fixed this errata by >>> hardware, add a new function to check the SVR_SOC_VER, SVR_MAJ and >>> SVR_MIN first, if the cpu is T2080 and version is not v1.0, doesn't run >>> the a007212 errata_workaround. >>> >>> Signed-off-by: Zhao Qiang <B45475@freescale.com> >>> --- >> >> >> Qiang, >> >> I don't agree with your analysis. >> >> This workaround has two parts. One part is to to disable DDR PLL in RCW. >> The second part is to detect DDR PLL is disabled and to implement the >> software workaround to bring DDR up. U-boot has the second part, it is >> safe to apply to all versions for affected SoC. I put in the comments. >> Your patch detects the SVR and decide if the workaround should be applied. >> This is wrong. It should detect if DDR PLL is disabled. In case an old >> RCW is used, you don't want to end up with a dead board because DDR is >> disabled. > > OK , got it , I will modify it for v2. > Thanks for you comment. > Qiang, I don't think you even need a patch for this. The logic for u-boot code is: Regardless of the SVR, the workaround is not be applied if RCW doesn't disable DDR PLL. Regardless of the SVR, the workaround is and should be applied if RCW disables DDR PLL. York
On 09/27/2014 12:02 AM, York Sun wrote: > -----Original Message----- > From: Sun York-R58495 > Sent: Saturday, September 27, 2014 12:02 AM > To: Zhao Qiang-B45475; u-boot@lists.denx.de > Cc: Xie Xiaobo-R63061 > Subject: Re: [PATCH 2/2] powerpc/mpc85xx: modify erratum A007212 > > On 09/25/2014 10:55 PM, Zhao Qiang-B45475 wrote: > > > > On 9/26/14 1:01 PM, York Sun wrote: > > > >> -----Original Message----- > >> From: Sun York-R58495 > >> Sent: Friday, September 26, 2014 1:01 PM > >> To: Zhao Qiang-B45475; u-boot@lists.denx.de > >> Cc: Xie Xiaobo-R63061; Zhao Qiang-B45475 > >> Subject: Re: [PATCH 2/2] powerpc/mpc85xx: modify erratum A007212 > >> > >> On 9/25/14 9:37 PM, "Zhao Qiang" <B45475@freescale.com> wrote: > >> > >>> T2080 v1.0 has this errata while v1.1 has fixed this errata by > >>> hardware, add a new function to check the SVR_SOC_VER, SVR_MAJ and > >>> SVR_MIN first, if the cpu is T2080 and version is not v1.0, doesn't > >>> run the a007212 errata_workaround. > >>> > >>> Signed-off-by: Zhao Qiang <B45475@freescale.com> > >>> --- > >> > >> > >> Qiang, > >> > >> I don't agree with your analysis. > >> > >> This workaround has two parts. One part is to to disable DDR PLL in > RCW. > >> The second part is to detect DDR PLL is disabled and to implement the > >> software workaround to bring DDR up. U-boot has the second part, it > >> is safe to apply to all versions for affected SoC. I put in the > comments. > >> Your patch detects the SVR and decide if the workaround should be > applied. > >> This is wrong. It should detect if DDR PLL is disabled. In case an > >> old RCW is used, you don't want to end up with a dead board because > >> DDR is disabled. > > > > OK , got it , I will modify it for v2. > > Thanks for you comment. > > > > Qiang, > > I don't think you even need a patch for this. The logic for u-boot code > is: > > Regardless of the SVR, the workaround is not be applied if RCW doesn't > disable DDR PLL. > Regardless of the SVR, the workaround is and should be applied if RCW > disables DDR PLL. And how about the file arch/powerpc/cpu/mpc85xx/speed.c. The code doesn't detect if the DDR PLL is disabled, it will config the mem_pll_rat. > > York Best Regards Zhao Qiang
On 9/27/14 6:56 PM, "Zhao Qiang-B45475" <qiang.zhao@freescale.com> wrote: >On 09/27/2014 12:02 AM, York Sun wrote: >> -----Original Message----- >> From: Sun York-R58495 >> Sent: Saturday, September 27, 2014 12:02 AM >> To: Zhao Qiang-B45475; u-boot@lists.denx.de >> Cc: Xie Xiaobo-R63061 >> Subject: Re: [PATCH 2/2] powerpc/mpc85xx: modify erratum A007212 >> >> On 09/25/2014 10:55 PM, Zhao Qiang-B45475 wrote: >> > >> > On 9/26/14 1:01 PM, York Sun wrote: >> > >> >> -----Original Message----- >> >> From: Sun York-R58495 >> >> Sent: Friday, September 26, 2014 1:01 PM >> >> To: Zhao Qiang-B45475; u-boot@lists.denx.de >> >> Cc: Xie Xiaobo-R63061; Zhao Qiang-B45475 >> >> Subject: Re: [PATCH 2/2] powerpc/mpc85xx: modify erratum A007212 >> >> >> >> On 9/25/14 9:37 PM, "Zhao Qiang" <B45475@freescale.com> wrote: >> >> >> >>> T2080 v1.0 has this errata while v1.1 has fixed this errata by >> >>> hardware, add a new function to check the SVR_SOC_VER, SVR_MAJ and >> >>> SVR_MIN first, if the cpu is T2080 and version is not v1.0, doesn't >> >>> run the a007212 errata_workaround. >> >>> >> >>> Signed-off-by: Zhao Qiang <B45475@freescale.com> >> >>> --- >> >> >> >> >> >> Qiang, >> >> >> >> I don't agree with your analysis. >> >> >> >> This workaround has two parts. One part is to to disable DDR PLL in >> RCW. >> >> The second part is to detect DDR PLL is disabled and to implement the >> >> software workaround to bring DDR up. U-boot has the second part, it >> >> is safe to apply to all versions for affected SoC. I put in the >> comments. >> >> Your patch detects the SVR and decide if the workaround should be >> applied. >> >> This is wrong. It should detect if DDR PLL is disabled. In case an >> >> old RCW is used, you don't want to end up with a dead board because >> >> DDR is disabled. >> > >> > OK , got it , I will modify it for v2. >> > Thanks for you comment. >> > >> >> Qiang, >> >> I don't think you even need a patch for this. The logic for u-boot code >> is: >> >> Regardless of the SVR, the workaround is not be applied if RCW doesn't >> disable DDR PLL. >> Regardless of the SVR, the workaround is and should be applied if RCW >> disables DDR PLL. > >And how about the file arch/powerpc/cpu/mpc85xx/speed.c. >The code doesn¹t detect if the DDR PLL is disabled, it will config the >mem_pll_rat. If you look closely in this file, you will see code guarded by macro CONFIG_SYS_FSL_ERRATUM_A007212. In case mem_pll_rat is detected as 0, a reserved field is used for DDR PLL ratio. It is written in erratum workaround. It wasn't in original document but should be updated a while ago. York >>
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 741eb63..a50bb08 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -121,7 +121,7 @@ static void check_erratum_a007212(void) { u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); - if (in_be32(plldgdcr) & 0x1fe) { + if (!not_has_erratum_a007212() && in_be32(plldgdcr) & 0x1fe) { /* check if PLL ratio is set by workaround */ puts("Work-around for Erratum A007212 enabled\n"); } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 78316a6..6219619 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -345,6 +345,8 @@ void fsl_erratum_a007212_workaround(void) u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); #endif #endif + if (not_has_erratum_a007212()) + return; /* * Even this workaround applies to selected version of SoCs, it is * safe to apply to all versions, with the limitation of odd ratios. diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 3236f6a..904d19d 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -13,6 +13,7 @@ #include <common.h> #include <ppc_asm.tmpl> #include <linux/compiler.h> +#include <asm/fsl_errata.h> #include <asm/processor.h> #include <asm/io.h> @@ -113,7 +114,7 @@ void get_sys_info(sys_info_t *sys_info) FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 - if (mem_pll_rat == 0) { + if (!not_has_erratum_a007212() && mem_pll_rat == 0) { mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index a977544..8f7777d 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -96,3 +96,17 @@ static inline bool not_has_erratum_a007186(void) return false; } #endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 +static inline bool not_has_erratum_a007212(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + if (((soc == SVR_T2080) && (SVR_MAJ(svr) > 1)) || + ((soc == SVR_T2080) && (SVR_MAJ(svr) == 1) && (SVR_MIN(svr) > 0))) + return true; + + return false; +} +#endif
T2080 v1.0 has this errata while v1.1 has fixed this errata by hardware, add a new function to check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first, if the cpu is T2080 and version is not v1.0, doesn't run the a007212 errata_workaround. Signed-off-by: Zhao Qiang <B45475@freescale.com> --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 ++ arch/powerpc/cpu/mpc85xx/speed.c | 3 ++- arch/powerpc/include/asm/fsl_errata.h | 14 ++++++++++++++ 4 files changed, 19 insertions(+), 2 deletions(-)