| Message ID | 1408641002-5376-1-git-send-email-fabio.estevam@freescale.com |
|---|---|
| State | Rejected |
| Delegated to: | Stefano Babic |
| Headers | show |
On Thursday, August 21, 2014 at 07:10:02 PM, Fabio Estevam wrote: > mx6 is an armv7 which has 64-byte cacheline size. > > Without this fix we are not able to get the FEC driver to work on mx6solox. > > 64-byte cacheline is also used by the kernel on ARMv7, so fix it > accordingly. It's not a kernel thing, it's architecture thing. Otherwise, Acked-by: Marek Vasut <marex@denx.de> Best regards, Marek Vasut
On Thu, Aug 21, 2014 at 2:14 PM, Marek Vasut <marex@denx.de> wrote: > On Thursday, August 21, 2014 at 07:10:02 PM, Fabio Estevam wrote: >> mx6 is an armv7 which has 64-byte cacheline size. >> >> Without this fix we are not able to get the FEC driver to work on mx6solox. >> >> 64-byte cacheline is also used by the kernel on ARMv7, so fix it >> accordingly. > > It's not a kernel thing, it's architecture thing. Otherwise, > > Acked-by: Marek Vasut <marex@denx.de> Yes, I mentioned the kernel just to provide an example. Maybe Stefano could remove this last sentence from the commit log when applying it, if he is happy with it, of course. Or I can send a v2 without it. Regards, Fabio Estevam
On Thu, Aug 21, 2014 at 2:14 PM, Marek Vasut <marex@denx.de> wrote: > On Thursday, August 21, 2014 at 07:10:02 PM, Fabio Estevam wrote: >> mx6 is an armv7 which has 64-byte cacheline size. >> >> Without this fix we are not able to get the FEC driver to work on mx6solox. >> >> 64-byte cacheline is also used by the kernel on ARMv7, so fix it >> accordingly. > > It's not a kernel thing, it's architecture thing. Otherwise, > > Acked-by: Marek Vasut <marex@denx.de> Actually the CortexA9 manual says: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Caccifbd.html "The cache line length is eight words." and the mx6q RM says: 12.5.4.1 L1 features .... • Eight 32-bit words per cache line So the current CONFIG_SYS_CACHELINE_SIZE of 32 is correct for mx6. In kernel we use 64-bytes of cache line for armv7 though: config ARM_L1_CACHE_SHIFT_6 bool default y if CPU_V7 help Setting ARM L1 cache line size to 64 Bytes.
Hi Fabio, On Thu, Aug 21, 2014 at 9:11 PM, Fabio Estevam <festevam@gmail.com> wrote: > On Thu, Aug 21, 2014 at 2:14 PM, Marek Vasut <marex@denx.de> wrote: >> On Thursday, August 21, 2014 at 07:10:02 PM, Fabio Estevam wrote: >>> mx6 is an armv7 which has 64-byte cacheline size. >>> >>> Without this fix we are not able to get the FEC driver to work on mx6solox. >>> >>> 64-byte cacheline is also used by the kernel on ARMv7, so fix it >>> accordingly. >> >> It's not a kernel thing, it's architecture thing. Otherwise, >> >> Acked-by: Marek Vasut <marex@denx.de> > > Actually the CortexA9 manual says: > http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Caccifbd.html > > "The cache line length is eight words." > > and the mx6q RM says: > > 12.5.4.1 L1 features > .... > • Eight 32-bit words per cache line > > So the current CONFIG_SYS_CACHELINE_SIZE of 32 is correct for mx6. Yes, it's always 32 bytes for Cortex-A9. But does mx6solox really have a standard Cortex-A9 core like all the currently released i.MX6 SoCs (which seems to be the case according to http://lwn.net/Articles/598434/), or a Cortex-A9 implementation with non-standard parameters tuned by Freescale, or even another core like a Cortex-A8? > In kernel we use 64-bytes of cache line for armv7 though: > > config ARM_L1_CACHE_SHIFT_6 > bool > default y if CPU_V7 > help > Setting ARM L1 cache line size to 64 Bytes. This seems to be used only for alignments, and stuff aligned with 64 bytes is also aligned with 32 bytes, so this should not matter. However, [1] reads the cache line size from the registers, and it does not use this constant. Regards, Benoît [1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/mm/cache-v7.S?id=refs/tags/v3.17-rc1
Hi Benoît, On Thu, Aug 21, 2014 at 5:13 PM, Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com> wrote: > Yes, it's always 32 bytes for Cortex-A9. But does mx6solox really have > a standard Cortex-A9 core like all the currently released i.MX6 SoCs > (which seems to be the case according to > http://lwn.net/Articles/598434/), or a Cortex-A9 implementation with > non-standard parameters tuned by Freescale, or even another core like > a Cortex-A8? It is a Cortex-A9 on mx6solox (there is also a Cortex-M4) and its manual also states 32 bytes of cache line. I am trying to get more information about the 64-bit alignment requirement on FEC RX DMA. Regards, Fabio Estevam
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 2631beb..e9e6f63 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -9,7 +9,7 @@ #define ARCH_MXC -#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_CACHELINE_SIZE 64 #define ROMCP_ARB_BASE_ADDR 0x00000000 #define ROMCP_ARB_END_ADDR 0x000FFFFF
mx6 is an armv7 which has 64-byte cacheline size. Without this fix we are not able to get the FEC driver to work on mx6solox. 64-byte cacheline is also used by the kernel on ARMv7, so fix it accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> --- arch/arm/include/asm/arch-mx6/imx-regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)