diff mbox

[U-Boot] iMX6: Disable the L2 before chaning the PL310 latency

Message ID 1408526304-27070-1-git-send-email-Ye.Li@freescale.com
State Awaiting Upstream
Delegated to: Stefano Babic
Headers show

Commit Message

Ye Li Aug. 20, 2014, 9:18 a.m. UTC 
From: "Ye.Li" <Ye.Li@freescale.com>

The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable. And
setting these registers must have PL310 NOT enabled.

But when using Plugin mode boot, the PL310 is enabled by bootrom.
The patch disables the PL310 before applying this setting.

Signed-off-by: Ye.Li <Ye.Li@freescale.com>
---
 arch/arm/cpu/armv7/mx6/soc.c |    3 +++
 1 file changed, 3 insertions(+)

Comments

Stefano Babic Sept. 9, 2014, 2:31 p.m. UTC | #1 
On 20/08/2014 11:18, Ye.Li wrote:
> From: "Ye.Li" <Ye.Li@freescale.com>
> 
> The Latency parameters of PL310 Tag RAM latency control register and
> Data RAM Latency control register are set in L2 cache enable. And
> setting these registers must have PL310 NOT enabled.
> 
> But when using Plugin mode boot, the PL310 is enabled by bootrom.
> The patch disables the PL310 before applying this setting.
> 
> Signed-off-by: Ye.Li <Ye.Li@freescale.com>
> ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index f20bdeb..cc2231a 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -394,6 +394,9 @@  void v7_outer_cache_enable(void)
 	}
 #endif
 
+	/* Must disable the L2 before changing the latency parameters */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
 	writel(0x132, &pl310->pl310_tag_latency_ctrl);
 	writel(0x132, &pl310->pl310_data_latency_ctrl);