| Message ID | 1385024402-23585-2-git-send-email-marc.zyngier@arm.com |
|---|---|
| State | Superseded |
| Delegated to: | Albert ARIBAUD |
| Headers | show |
Hello Marc > + .align 5 @ Minimal alignment for vectors > + > /* the vector table for secure state and HYP mode */ > _monitor_vectors: > .word 0 /* reset */ > @@ -32,7 +34,6 @@ _monitor_vectors: > * to non-secure state. > * We use only r0 and r1 here, due to constraints in the caller. > */ > - .align 5 > _secure_monitor: > mrc p15, 0, r1, c1, c1, 0 @ read SCR > bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits Correct. I had posted a patch to fix this problem. http://patchwork.ozlabs.org/patch/280915/ But it have not been appiled yet. Best Regards Masahiro Yamada
Hi Masahiro, On 21/11/13 10:19, Masahiro Yamada wrote: > Hello Marc > >> + .align 5 @ Minimal alignment for vectors >> + >> /* the vector table for secure state and HYP mode */ >> _monitor_vectors: >> .word 0 /* reset */ >> @@ -32,7 +34,6 @@ _monitor_vectors: >> * to non-secure state. >> * We use only r0 and r1 here, due to constraints in the caller. >> */ >> - .align 5 >> _secure_monitor: >> mrc p15, 0, r1, c1, c1, 0 @ read SCR >> bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits > > Correct. > > I had posted a patch to fix this problem. > http://patchwork.ozlabs.org/patch/280915/ > But it have not been appiled yet. How comes nobody cares about it? This is really a nasty one to track down, as it completely depends on the surrounding objects. /me puzzled. M.
On 11/21/2013 09:59 AM, Marc Zyngier wrote: > Make sure the vectors are aligned on a 32 byte boundary, not > the code that deals with it... I think that patch was posted before, and I already acked it, but it didn't make it into some tree. Albert, can you please take this? Also a candidate for the stable tree. > > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Andre Przywara <andre.przywara@linaro.org> Regards, Andre. > --- > arch/arm/cpu/armv7/nonsec_virt.S | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S > index 24b4c18..29987cd 100644 > --- a/arch/arm/cpu/armv7/nonsec_virt.S > +++ b/arch/arm/cpu/armv7/nonsec_virt.S > @@ -14,6 +14,8 @@ > .arch_extension sec > .arch_extension virt > > + .align 5 @ Minimal alignment for vectors > + > /* the vector table for secure state and HYP mode */ > _monitor_vectors: > .word 0 /* reset */ > @@ -32,7 +34,6 @@ _monitor_vectors: > * to non-secure state. > * We use only r0 and r1 here, due to constraints in the caller. > */ > - .align 5 > _secure_monitor: > mrc p15, 0, r1, c1, c1, 0 @ read SCR > bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits >
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 24b4c18..29987cd 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -14,6 +14,8 @@ .arch_extension sec .arch_extension virt + .align 5 @ Minimal alignment for vectors + /* the vector table for secure state and HYP mode */ _monitor_vectors: .word 0 /* reset */ @@ -32,7 +34,6 @@ _monitor_vectors: * to non-secure state. * We use only r0 and r1 here, due to constraints in the caller. */ - .align 5 _secure_monitor: mrc p15, 0, r1, c1, c1, 0 @ read SCR bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits
Make sure the vectors are aligned on a 32 byte boundary, not the code that deals with it... Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- arch/arm/cpu/armv7/nonsec_virt.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)