diff mbox

[U-Boot] powerpc/85xx: Add workaround for erratum CPU-A011 on e500mc cores

Message ID 1314443032-2811-1-git-send-email-galak@kernel.crashing.org
State Changes Requested
Headers show

Commit Message

Kumar Gala Aug. 27, 2011, 11:03 a.m. UTC
Issue:
CoreNet bad data signal is not sent with shared data from L1 Data Cache
when it has an error

Workaround:
Run in write-shadow mode by setting L1CSR2[DCWS] = 1

By default we do NOT enable this, thus we have #undef in
config_mpc85xx.h for this erratum.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    3 +++
 arch/powerpc/cpu/mpc85xx/cpu_init.c       |    3 ++-
 arch/powerpc/cpu/mpc85xx/release.S        |    3 ++-
 arch/powerpc/include/asm/config_mpc85xx.h |    3 +++
 4 files changed, 10 insertions(+), 2 deletions(-)

Comments

Wolfgang Denk Aug. 27, 2011, 11:36 a.m. UTC | #1
Dear Kumar Gala,

In message <1314443032-2811-1-git-send-email-galak@kernel.crashing.org> you wrote:
> Issue:
> CoreNet bad data signal is not sent with shared data from L1 Data Cache
> when it has an error
> 
> Workaround:
> Run in write-shadow mode by setting L1CSR2[DCWS] = 1
> 
> By default we do NOT enable this, thus we have #undef in
> config_mpc85xx.h for this erratum.

NAK.  Please do not undef what is not defined anyway.

Best regards,

Wolfgang Denk
Kumar Gala Aug. 27, 2011, 12:01 p.m. UTC | #2
On Aug 27, 2011, at 6:36 AM, Wolfgang Denk wrote:

> Dear Kumar Gala,
> 
> In message <1314443032-2811-1-git-send-email-galak@kernel.crashing.org> you wrote:
>> Issue:
>> CoreNet bad data signal is not sent with shared data from L1 Data Cache
>> when it has an error
>> 
>> Workaround:
>> Run in write-shadow mode by setting L1CSR2[DCWS] = 1
>> 
>> By default we do NOT enable this, thus we have #undef in
>> config_mpc85xx.h for this erratum.
> 
> NAK.  Please do not undef what is not defined anyway.
> 
> Best regards,
> 
> Wolfgang Denk

Any suggestions on how to do this? - comment it out?

/* #define CONFIG_SYS_FSL_ERRATUM_CPU_E500MC_A011 */

- k
Wolfgang Denk Aug. 27, 2011, 1:41 p.m. UTC | #3
Dear Kumar Gala,

In message <8D21ECF0-CB7E-4DDE-9F18-E1828FF5E8C2@kernel.crashing.org> you wrote:
> 
> Any suggestions on how to do this? - comment it out?
> 
> /* #define CONFIG_SYS_FSL_ERRATUM_CPU_E500MC_A011 */

That would be dead code.

You don't want to add all possible #defines to your config files, do
you?  This is not a good weay to document your code.

Apropos documentation - I did not see that you explain
CONFIG_SYS_FSL_ERRATUM_CPU_E500MC_A011 (or any other of the ton of
CONFIG_SYS_FSL_ERRATUM_* you have) in the readme, or elsewehere.

_This_ is what you should fix.

Best regards,

Wolfgang Denk
Kumar Gala Aug. 27, 2011, 4:09 p.m. UTC | #4
On Aug 27, 2011, at 8:41 AM, Wolfgang Denk wrote:

> Dear Kumar Gala,
> 
> In message <8D21ECF0-CB7E-4DDE-9F18-E1828FF5E8C2@kernel.crashing.org> you wrote:
>> 
>> Any suggestions on how to do this? - comment it out?
>> 
>> /* #define CONFIG_SYS_FSL_ERRATUM_CPU_E500MC_A011 */
> 
> That would be dead code.
> 
> You don't want to add all possible #defines to your config files, do
> you?  This is not a good weay to document your code.

Gotcha.

> 
> Apropos documentation - I did not see that you explain
> CONFIG_SYS_FSL_ERRATUM_CPU_E500MC_A011 (or any other of the ton of
> CONFIG_SYS_FSL_ERRATUM_* you have) in the readme, or elsewehere.
> 
> _This_ is what you should fix.

I'll add a general comment about CONFIG_SYS_FSL_ERRATUM_* in README and a new doc/README.fsl-ppc-errata if that sounds good.

- k
Wolfgang Denk Aug. 27, 2011, 5:08 p.m. UTC | #5
Dear Kumar Gala,

In message <1A241F20-4DDB-4A57-8590-30735E9665A9@kernel.crashing.org> you wrote:
> 
> I'll add a general comment about CONFIG_SYS_FSL_ERRATUM_* in README and
> a new doc/README.fsl-ppc-errata if that sounds good.

Thanks, appreciated.

Best regards,

Wolfgang Denk
diff mbox

Patch

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 49f03f1..47bb0d2 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -53,6 +53,9 @@  static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
 	puts("Work-around for Erratum CPU22 enabled\n");
 #endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_E500MC_A011)
+	puts("Work-around for Erratum CPU-A011 enabled\n");
+#endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
 	puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index f1ab28b..a32cada 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -305,7 +305,8 @@  int cpu_init_r(void)
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 #endif
 
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
+    defined(CONFIG_SYS_FSL_ERRATUM_CPU_E500MC_A011)
 	flush_dcache();
 	mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
 	sync();
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 6678ed4..272b3e6 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -137,7 +137,8 @@  __secondary_start_page:
 	mtspr	L1CSR2,r8
 #endif
 
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
+    defined(CONFIG_SYS_FSL_ERRATUM_CPU_E500MC_A011)
 	mfspr	r8,L1CSR2
 	oris	r8,r8,(L1CSR2_DCWS)@h
 	mtspr	L1CSR2,r8
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index ff93367..484654c 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -311,6 +311,7 @@ 
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#undef CONFIG_SYS_FSL_ERRATUM_CPU_E500MC_A011
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_USBxx
 
@@ -330,6 +331,7 @@ 
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#undef CONFIG_SYS_FSL_ERRATUM_CPU_E500MC_A011
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_USBxx
 
@@ -349,6 +351,7 @@ 
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#undef CONFIG_SYS_FSL_ERRATUM_CPU_E500MC_A011
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_USBxx