diff mbox

[U-Boot,v2,3/6] imx: Add support for USB EHCI on imx25

Message ID 1309948113-12971-4-git-send-email-weisserm@arcor.de
State Accepted
Commit dddb7c9ffdb3813c1242aa43b935dd3484c53a35
Delegated to: Stefano Babic
Headers show

Commit Message

Matthias Weisser July 6, 2011, 10:28 a.m. UTC 
Adding support for USB host on imx25 using the internal PHY. Changing the name
of base address define for imx31 to get some unification.

Signed-off-by: Matthias Weisser <weisserm@arcor.de>
---
Changes in v2:
  - Partially unified for imx25 and imx31
  
 arch/arm/include/asm/arch-mx31/imx-regs.h |    2 +-
 drivers/usb/host/ehci-mxc.c               |   33 ++++++++++++++++++++++-------
 2 files changed, 26 insertions(+), 9 deletions(-)

Comments

Stefano Babic July 13, 2011, 11:34 a.m. UTC | #1 
On 07/06/2011 12:28 PM, Matthias Weisser wrote:
> Adding support for USB host on imx25 using the internal PHY. Changing the name
> of base address define for imx31 to get some unification.
> 
> Signed-off-by: Matthias Weisser <weisserm@arcor.de>

Applied to u-boot-imx, thanks

Best regards,
Stefano Babic
diff mbox

Patch

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 306f966..3c8d607 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -746,7 +746,7 @@  enum iomux_pins {
 #define IRAM_SIZE	(16 * 1024)
 
 #define MX31_AIPS1_BASE_ADDR	0x43f00000
-#define MX31_OTG_BASE_ADDR	(MX31_AIPS1_BASE_ADDR + 0x88000)
+#define IMX_USB_BASE		(MX31_AIPS1_BASE_ADDR + 0x88000)
 
 /* USB portsc */
 /* values for portsc field */
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index 6af35ab..a0cfbb7 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -29,6 +29,14 @@ 
 
 #define USBCTRL_OTGBASE_OFFSET	0x600
 
+#ifdef CONFIG_MX25
+#define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
+#define MX25_USB_CTRL_HSTD_BIT		(1<<5)
+#define MX25_USB_CTRL_USBTE_BIT		(1<<4)
+#define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
+#endif
+
+#ifdef CONFIG_MX31
 #define MX31_OTG_SIC_SHIFT	29
 #define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
 #define MX31_OTG_PM_BIT		(1 << 24)
@@ -42,12 +50,19 @@ 
 #define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
 #define MX31_H1_PM_BIT		(1 << 8)
 #define MX31_H1_DT_BIT		(1 << 4)
+#endif
 
 static int mxc_set_usbcontrol(int port, unsigned int flags)
 {
 	unsigned int v;
+
+#ifdef CONFIG_MX25
+	v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
+		MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
+#endif
+
 #ifdef CONFIG_MX31
-		v = readl(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET);
+		v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
 
 		switch (port) {
 		case 0:	/* OTG port */
@@ -85,36 +100,38 @@  static int mxc_set_usbcontrol(int port, unsigned int flags)
 		default:
 			return -EINVAL;
 		}
-
-		writel(v, MX31_OTG_BASE_ADDR +
-				     USBCTRL_OTGBASE_OFFSET);
 #endif
-		return 0;
+
+	writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+	return 0;
 }
 
 int ehci_hcd_init(void)
 {
-	u32 tmp;
 	struct usb_ehci *ehci;
+#ifdef CONFIG_MX31
+	u32 tmp;
 	struct clock_control_regs *sc_regs =
 		(struct clock_control_regs *)CCM_BASE;
 
 	tmp = __raw_readl(&sc_regs->ccmr);
 	__raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ;
+#endif
 
 	udelay(80);
 
 	/* Take USB2 */
-	ehci = (struct usb_ehci *)(MX31_OTG_BASE_ADDR +
+	ehci = (struct usb_ehci *)(IMX_USB_BASE +
 		(0x200 * CONFIG_MXC_USB_PORT));
 	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
 	hcor = (struct ehci_hcor *)((uint32_t) hccr +
 			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
 	setbits_le32(&ehci->usbmode, CM_HOST);
+#ifdef CONFIG_MX31
 	setbits_le32(&ehci->control, USB_EN);
 
 	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
-
+#endif
 	mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
 
 	udelay(10000);