| Message ID | 1306353067-24975-1-git-send-email-cook@isgchips.com |
|---|---|
| State | Accepted |
| Commit | 810cb19003ffe0115d10700fc512a2a743916f20 |
| Headers | show |
On Wed, 25 May 2011 15:51:07 -0400 Bill Cook <cook@isgchips.com> wrote: > On a 8308 based board it was found that the PEX_GLK_RATIO register > (programmed in arch/powerpc/cpu/mpc83xx/pcie.c) was getting set to 0, This > was tracked to the fact that the pci express clock frequency was not being > assigned to the pciexp1_clk entry in the global data structure in file > arch/powerpc/cpu/mpc83xx/speed.c. Fix this and a similiar issue in > 'do_clocks' command. > > Signed-off-by: Bill Cook <cook@isgchips.com> > --- applied to u-boot-mpc83xx. Thanks, Kim
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 5e616dd..86d2e18 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -481,7 +481,8 @@ int get_clocks(void) gd->qe_clk = qe_clk; gd->brg_clk = brg_clk; #endif -#if defined(CONFIG_MPC837x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC837x) gd->pciexp1_clk = pciexp1_clk; gd->pciexp2_clk = pciexp2_clk; #endif @@ -541,7 +542,8 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_MPC834x) printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk)); #endif -#if defined(CONFIG_MPC837x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC837x) printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk)); printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk)); #endif
On a 8308 based board it was found that the PEX_GLK_RATIO register (programmed in arch/powerpc/cpu/mpc83xx/pcie.c) was getting set to 0, This was tracked to the fact that the pci express clock frequency was not being assigned to the pciexp1_clk entry in the global data structure in file arch/powerpc/cpu/mpc83xx/speed.c. Fix this and a similiar issue in 'do_clocks' command. Signed-off-by: Bill Cook <cook@isgchips.com> --- This also points to another problem. The description of the PEX_CLK_RATIO for the various SOCs in question (I checked the RMs for 8308, 8315, and 8378) shows a different maximum freqency for the PCIe core. So the divider in the equation on line 271 should reflect these differences. This seems to be the only mention of a maximum core frequency though, so I hesitate to patch pcie.c without feedback from Freescale. As I'm not a PCI expert, I would rather someone at Freescale look at this and provide appropriate patches. Also, if the max PCIe core frequency on the 8308 is really 125MHz, shouldn't the SCCR PCIEXPCM field of the SCCR be programmed with a 2 instead of 1, this is given by the definition of CONFIG_SYS_SCCR_PCIEXP1CM in the board config file. arch/powerpc/cpu/mpc83xx/speed.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-)