| Message ID | 1265509186-14826-2-git-send-email-siarhei.siamashka@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Sandeep Paulraj |
| Headers | show |
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index 7b78fa4..b9b71dc 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -140,8 +140,6 @@ void setup_auxcr() */ __asm__ __volatile__("mov r12, #0x3"); __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - /* Enabling ASA */ - __asm__ __volatile__("orr r0, r0, #0x10"); /* Enable L1NEON */ __asm__ __volatile__("orr r0, r0, #1 << 5"); /* SMI instruction to call ROM Code API */
Setting ASA bit hurts performance for the code which has lots of I-cache misses and there are no Cortex-A8 errata workarounds which would require to have it. A test program which intentionally stresses I-cache misses on conditional branches is attached. ASA bit is not set: real 0m2.940s user 0m2.930s sys 0m0.008s ASA bit is set: real 0m3.470s user 0m3.461s sys 0m0.008s The difference on some real applications is much more modest and is just something like ~0.5%, but every little bit helps. /**** start of bench_ASA.c ****/ void __attribute__((naked)) f(int count, void *rand) { asm volatile ( " push {r4, r5, r6, lr}\n" " mov r4, r0\n" " mov r5, r1\n" "0:\n" ".rept 4096\n" " blx r5\n" " tst r0, #1\n" " bne 1f\n" " b 2f\n" ".balign 64\n" "1:\n" ".rept 15\n" " add r0, r0, #0\n" ".endr\n" " b 3f\n" ".balign 64\n" "2:\n" ".rept 16\n" " add r0, r0, #0\n" ".endr\n" "3:\n" ".endr\n" " subs r4, r4, #1\n" " bgt 0b\n" " pop {r4, r5, r6, pc}\n" ); } int main() { f(1000, rand); return 0; } /**** end of bench_ASA.c ****/ Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> --- cpu/arm_cortexa8/omap3/board.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-)