Message ID | 20230509082617.119018-1-minda.chen@starfivetech.com |
---|---|
Headers | show |
Series | Add StarFive JH7110 PCIe drvier support | expand |
Hi Rick and Leo Could you review these series patches? Thanks. Since patch 1 was acked by Pali, Does it mean patch 1 is accepted? On 2023/5/9 16:26, Minda Chen wrote: > These PCIe series patches are based on the JH7110 RISC-V SoC and VisionFive V2 board. > > The PCIe driver depends on gpio, pinctrl, clk and reset driver to do init. > The PCIe dts configuation includes all these setting. > > The PCIe drivers codes has been tested on the VisionFive V2 boards. > The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet adapter. > > previous patch version > > v1: https://patchwork.ozlabs.org/project/uboot/cover/20230223105240.15180-1-minda.chen@starfivetech.com/ > v2: https://patchwork.ozlabs.org/project/uboot/cover/20230308054833.95730-1-minda.chen@starfivetech.com/ > v3: https://patchwork.ozlabs.org/project/uboot/cover/20230329100143.10724-1-minda.chen@starfivetech.com/ > v4: https://patchwork.ozlabs.org/project/uboot/cover/20230411010209.76561-1-minda.chen@starfivetech.com/ > v5: https://patchwork.ozlabs.org/project/uboot/cover/20230423105859.125764-1-minda.chen@starfivetech.com/ > > changes > v6 > patch 2 > 1. Change one VisionFive2 config file. > patch 3 > 1. remove the pcie interrupt-controller. interrupts setting revert to origin. > > setting. > v5 > patch 1 > 1. split PLDA controller driver codes to pcie_plda_common.c > 2. correct the codes of record secondary number. > patch 3 > 1. change the pcie dtsi config. make them the same with kernel. > > v4 > patch 1 > 1. Remove the IDS_REVISION_ID macros. > 2. Replace sec_busno to first_busno in starfive_pcie > 3. Remove starfive_pcie_off_conf function. > 4. Replace "imply" to "depends on" in PCIe Kconfig. > 5 .Check sec_busno in starfive_pcie_addr_valid. > > v3 > patch 1 > 1. remove the read vendor ID delay > 2. remove starfive_pcie_hide_rc_bar function. do not hide host > bridge BAR write. > 3. Using PCIE_ECAM_OFFSET and PCI_CLASS_BRIDGE_PCI_NORMAL macros. > 4. Add comments for bus and address limitation reason in function > starfive_pcie_addr_valid > 5. Change the multiple line comments in Line 373 > 6. Using gpio_request_by_name to get PCIe reset gpio,and using > dm_gpio_set_value set GPIO value. > patch 2 > 1. support PCIeboth 12a and 13b vf2 board. > patch 3 > 1. reset dts change to reset-gpio. > > v2 > 1. remove clock commit. The pcie clocks change has been includeded in [1]. > 2. Using GENMASK marco1 in patch1. > 3. remove the syscon dts node in patch3. The syscon dts dts node has been > included in [1]. > > > Mason Huo (3): > starfive: pci: Add StarFive JH7110 pcie driver > configs: starfive-jh7110: Add support for PCIe host driver > riscv: dts: starfive: Enable PCIe host controller > > .../dts/jh7110-starfive-visionfive-2.dtsi | 11 + > arch/riscv/dts/jh7110.dtsi | 74 ++++ > configs/starfive_visionfive2_defconfig | 10 + > drivers/pci/Kconfig | 13 + > drivers/pci/Makefile | 2 + > drivers/pci/pcie_plda_common.c | 116 +++++++ > drivers/pci/pcie_plda_common.h | 118 +++++++ > drivers/pci/pcie_starfive_jh7110.c | 317 ++++++++++++++++++ > 8 files changed, 661 insertions(+) > create mode 100644 drivers/pci/pcie_plda_common.c > create mode 100644 drivers/pci/pcie_plda_common.h > create mode 100644 drivers/pci/pcie_starfive_jh7110.c > > > base-commit: c9c2c95d4cd27fe0cd41fe13a863899d268f973c
Hi Minda > From: Minda Chen <minda.chen@starfivetech.com> > Sent: Thursday, June 01, 2023 9:07 AM > To: Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Simon Glass <sjg@chromium.org>; Stefan Roese <sr@denx.de>; Andrew Scull <ascull@google.com>; Pali Rohár <pali@kernel.org>; Mark Kettenis <kettenis@openbsd.org> > Cc: u-boot@lists.denx.de; Mason Huo <mason.huo@starfivetech.com>; Leyfoon Tan <leyfoon.tan@starfivetech.com>; Kevin Xie <kevin.xie@starfivetech.com> > Subject: Re: [PATCH v6 0/3] Add StarFive JH7110 PCIe drvier support > > > Hi Rick and Leo > Could you review these series patches? Thanks. > Since patch 1 was acked by Pali, Does it mean patch 1 is accepted? OK, we will review these series patches ASAP and help to push. Thanks, Rick > > On 2023/5/9 16:26, Minda Chen wrote: > > These PCIe series patches are based on the JH7110 RISC-V SoC and VisionFive V2 board. > > > > The PCIe driver depends on gpio, pinctrl, clk and reset driver to do init. > > The PCIe dts configuation includes all these setting. > > > > The PCIe drivers codes has been tested on the VisionFive V2 boards. > > The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet adapter. > > > > previous patch version > > > > v1: > > https://patchwork.ozlabs.org/project/uboot/cover/20230223105240.15180- > > 1-minda.chen@starfivetech.com/ > > v2: > > https://patchwork.ozlabs.org/project/uboot/cover/20230308054833.95730- > > 1-minda.chen@starfivetech.com/ > > v3: > > https://patchwork.ozlabs.org/project/uboot/cover/20230329100143.10724- > > 1-minda.chen@starfivetech.com/ > > v4: > > https://patchwork.ozlabs.org/project/uboot/cover/20230411010209.76561- > > 1-minda.chen@starfivetech.com/ > > v5: > > https://patchwork.ozlabs.org/project/uboot/cover/20230423105859.125764 > > -1-minda.chen@starfivetech.com/ > > > > changes > > v6 > > patch 2 > > 1. Change one VisionFive2 config file. > > patch 3 > > 1. remove the pcie interrupt-controller. interrupts setting revert to origin. > > > > setting. > > v5 > > patch 1 > > 1. split PLDA controller driver codes to pcie_plda_common.c > > 2. correct the codes of record secondary number. > > patch 3 > > 1. change the pcie dtsi config. make them the same with kernel. > > > > v4 > > patch 1 > > 1. Remove the IDS_REVISION_ID macros. > > 2. Replace sec_busno to first_busno in starfive_pcie > > 3. Remove starfive_pcie_off_conf function. > > 4. Replace "imply" to "depends on" in PCIe Kconfig. > > 5 .Check sec_busno in starfive_pcie_addr_valid. > > > > v3 > > patch 1 > > 1. remove the read vendor ID delay > > 2. remove starfive_pcie_hide_rc_bar function. do not hide host > > bridge BAR write. > > 3. Using PCIE_ECAM_OFFSET and PCI_CLASS_BRIDGE_PCI_NORMAL macros. > > 4. Add comments for bus and address limitation reason in function > > starfive_pcie_addr_valid > > 5. Change the multiple line comments in Line 373 > > 6. Using gpio_request_by_name to get PCIe reset gpio,and using > > dm_gpio_set_value set GPIO value. > > patch 2 > > 1. support PCIeboth 12a and 13b vf2 board. > > patch 3 > > 1. reset dts change to reset-gpio. > > > > v2 > > 1. remove clock commit. The pcie clocks change has been includeded in [1]. > > 2. Using GENMASK marco1 in patch1. > > 3. remove the syscon dts node in patch3. The syscon dts dts node has been > > included in [1]. > > > > > > Mason Huo (3): > > starfive: pci: Add StarFive JH7110 pcie driver > > configs: starfive-jh7110: Add support for PCIe host driver > > riscv: dts: starfive: Enable PCIe host controller > > > > .../dts/jh7110-starfive-visionfive-2.dtsi | 11 + > > arch/riscv/dts/jh7110.dtsi | 74 ++++ > > configs/starfive_visionfive2_defconfig | 10 + > > drivers/pci/Kconfig | 13 + > > drivers/pci/Makefile | 2 + > > drivers/pci/pcie_plda_common.c | 116 +++++++ > > drivers/pci/pcie_plda_common.h | 118 +++++++ > > drivers/pci/pcie_starfive_jh7110.c | 317 ++++++++++++++++++ > > 8 files changed, 661 insertions(+) > > create mode 100644 drivers/pci/pcie_plda_common.c create mode 100644 > > drivers/pci/pcie_plda_common.h create mode 100644 > > drivers/pci/pcie_starfive_jh7110.c > > > > > > base-commit: c9c2c95d4cd27fe0cd41fe13a863899d268f973c
Hi Minda, On Thu, Jun 01, 2023 at 09:07:14AM +0800, Minda Chen wrote: > > Hi Rick and Leo > Could you review these series patches? Thanks. > Since patch 1 was acked by Pali, Does it mean patch 1 is accepted? I think acked-by means that the patch is considered good enough to be merged. Aside from that, your patchset caused CI error by enabling the RTL8169 driver. Could you take a look at it ? (https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/638021) It's mostly compilation warnings that are being treated as errors. The patchset looks good to me, I could merge the patchset as soon as the CI errors are fixed! Thanks & best regards, Leo > On 2023/5/9 16:26, Minda Chen wrote: > > These PCIe series patches are based on the JH7110 RISC-V SoC and VisionFive V2 board. > > > > The PCIe driver depends on gpio, pinctrl, clk and reset driver to do init. > > The PCIe dts configuation includes all these setting. > > > > The PCIe drivers codes has been tested on the VisionFive V2 boards. > > The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet adapter. > > > > previous patch version > > > > v1: https://patchwork.ozlabs.org/project/uboot/cover/20230223105240.15180-1-minda.chen@starfivetech.com/ > > v2: https://patchwork.ozlabs.org/project/uboot/cover/20230308054833.95730-1-minda.chen@starfivetech.com/ > > v3: https://patchwork.ozlabs.org/project/uboot/cover/20230329100143.10724-1-minda.chen@starfivetech.com/ > > v4: https://patchwork.ozlabs.org/project/uboot/cover/20230411010209.76561-1-minda.chen@starfivetech.com/ > > v5: https://patchwork.ozlabs.org/project/uboot/cover/20230423105859.125764-1-minda.chen@starfivetech.com/ > > > > changes > > v6 > > patch 2 > > 1. Change one VisionFive2 config file. > > patch 3 > > 1. remove the pcie interrupt-controller. interrupts setting revert to origin. > > > > setting. > > v5 > > patch 1 > > 1. split PLDA controller driver codes to pcie_plda_common.c > > 2. correct the codes of record secondary number. > > patch 3 > > 1. change the pcie dtsi config. make them the same with kernel. > > > > v4 > > patch 1 > > 1. Remove the IDS_REVISION_ID macros. > > 2. Replace sec_busno to first_busno in starfive_pcie > > 3. Remove starfive_pcie_off_conf function. > > 4. Replace "imply" to "depends on" in PCIe Kconfig. > > 5 .Check sec_busno in starfive_pcie_addr_valid. > > > > v3 > > patch 1 > > 1. remove the read vendor ID delay > > 2. remove starfive_pcie_hide_rc_bar function. do not hide host > > bridge BAR write. > > 3. Using PCIE_ECAM_OFFSET and PCI_CLASS_BRIDGE_PCI_NORMAL macros. > > 4. Add comments for bus and address limitation reason in function > > starfive_pcie_addr_valid > > 5. Change the multiple line comments in Line 373 > > 6. Using gpio_request_by_name to get PCIe reset gpio,and using > > dm_gpio_set_value set GPIO value. > > patch 2 > > 1. support PCIeboth 12a and 13b vf2 board. > > patch 3 > > 1. reset dts change to reset-gpio. > > > > v2 > > 1. remove clock commit. The pcie clocks change has been includeded in [1]. > > 2. Using GENMASK marco1 in patch1. > > 3. remove the syscon dts node in patch3. The syscon dts dts node has been > > included in [1]. > > > > > > Mason Huo (3): > > starfive: pci: Add StarFive JH7110 pcie driver > > configs: starfive-jh7110: Add support for PCIe host driver > > riscv: dts: starfive: Enable PCIe host controller > > > > .../dts/jh7110-starfive-visionfive-2.dtsi | 11 + > > arch/riscv/dts/jh7110.dtsi | 74 ++++ > > configs/starfive_visionfive2_defconfig | 10 + > > drivers/pci/Kconfig | 13 + > > drivers/pci/Makefile | 2 + > > drivers/pci/pcie_plda_common.c | 116 +++++++ > > drivers/pci/pcie_plda_common.h | 118 +++++++ > > drivers/pci/pcie_starfive_jh7110.c | 317 ++++++++++++++++++ > > 8 files changed, 661 insertions(+) > > create mode 100644 drivers/pci/pcie_plda_common.c > > create mode 100644 drivers/pci/pcie_plda_common.h > > create mode 100644 drivers/pci/pcie_starfive_jh7110.c > > > > > > base-commit: c9c2c95d4cd27fe0cd41fe13a863899d268f973c
On 2023/6/16 16:42, Leo Liang wrote: > Hi Minda, > > On Thu, Jun 01, 2023 at 09:07:14AM +0800, Minda Chen wrote: >> >> Hi Rick and Leo >> Could you review these series patches? Thanks. >> Since patch 1 was acked by Pali, Does it mean patch 1 is accepted? > > I think acked-by means that the patch is considered good enough to be merged. > > Aside from that, your patchset caused CI error by enabling the RTL8169 driver. > Could you take a look at it ? (https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/638021) > It's mostly compilation warnings that are being treated as errors. > The patchset looks good to me, I could merge the patchset as soon as the CI errors are fixed! > > Thanks & best regards, > Leo > Thanks. I will commit another patch to fix the warning. >> On 2023/5/9 16:26, Minda Chen wrote: >> > These PCIe series patches are based on the JH7110 RISC-V SoC and VisionFive V2 board. >> > >> > The PCIe driver depends on gpio, pinctrl, clk and reset driver to do init. >> > The PCIe dts configuation includes all these setting. >> > >> > The PCIe drivers codes has been tested on the VisionFive V2 boards. >> > The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet adapter. >> > >> > previous patch version >> > >> > v1: https://patchwork.ozlabs.org/project/uboot/cover/20230223105240.15180-1-minda.chen@starfivetech.com/ >> > v2: https://patchwork.ozlabs.org/project/uboot/cover/20230308054833.95730-1-minda.chen@starfivetech.com/ >> > v3: https://patchwork.ozlabs.org/project/uboot/cover/20230329100143.10724-1-minda.chen@starfivetech.com/ >> > v4: https://patchwork.ozlabs.org/project/uboot/cover/20230411010209.76561-1-minda.chen@starfivetech.com/ >> > v5: https://patchwork.ozlabs.org/project/uboot/cover/20230423105859.125764-1-minda.chen@starfivetech.com/ >> > >> > changes >> > v6 >> > patch 2 >> > 1. Change one VisionFive2 config file. >> > patch 3 >> > 1. remove the pcie interrupt-controller. interrupts setting revert to origin. >> > >> > setting. >> > v5 >> > patch 1 >> > 1. split PLDA controller driver codes to pcie_plda_common.c >> > 2. correct the codes of record secondary number. >> > patch 3 >> > 1. change the pcie dtsi config. make them the same with kernel. >> > >> > v4 >> > patch 1 >> > 1. Remove the IDS_REVISION_ID macros. >> > 2. Replace sec_busno to first_busno in starfive_pcie >> > 3. Remove starfive_pcie_off_conf function. >> > 4. Replace "imply" to "depends on" in PCIe Kconfig. >> > 5 .Check sec_busno in starfive_pcie_addr_valid. >> > >> > v3 >> > patch 1 >> > 1. remove the read vendor ID delay >> > 2. remove starfive_pcie_hide_rc_bar function. do not hide host >> > bridge BAR write. >> > 3. Using PCIE_ECAM_OFFSET and PCI_CLASS_BRIDGE_PCI_NORMAL macros. >> > 4. Add comments for bus and address limitation reason in function >> > starfive_pcie_addr_valid >> > 5. Change the multiple line comments in Line 373 >> > 6. Using gpio_request_by_name to get PCIe reset gpio,and using >> > dm_gpio_set_value set GPIO value. >> > patch 2 >> > 1. support PCIeboth 12a and 13b vf2 board. >> > patch 3 >> > 1. reset dts change to reset-gpio. >> > >> > v2 >> > 1. remove clock commit. The pcie clocks change has been includeded in [1]. >> > 2. Using GENMASK marco1 in patch1. >> > 3. remove the syscon dts node in patch3. The syscon dts dts node has been >> > included in [1]. >> > >> > >> > Mason Huo (3): >> > starfive: pci: Add StarFive JH7110 pcie driver >> > configs: starfive-jh7110: Add support for PCIe host driver >> > riscv: dts: starfive: Enable PCIe host controller >> > >> > .../dts/jh7110-starfive-visionfive-2.dtsi | 11 + >> > arch/riscv/dts/jh7110.dtsi | 74 ++++ >> > configs/starfive_visionfive2_defconfig | 10 + >> > drivers/pci/Kconfig | 13 + >> > drivers/pci/Makefile | 2 + >> > drivers/pci/pcie_plda_common.c | 116 +++++++ >> > drivers/pci/pcie_plda_common.h | 118 +++++++ >> > drivers/pci/pcie_starfive_jh7110.c | 317 ++++++++++++++++++ >> > 8 files changed, 661 insertions(+) >> > create mode 100644 drivers/pci/pcie_plda_common.c >> > create mode 100644 drivers/pci/pcie_plda_common.h >> > create mode 100644 drivers/pci/pcie_starfive_jh7110.c >> > >> > >> > base-commit: c9c2c95d4cd27fe0cd41fe13a863899d268f973c