mbox series

[U-Boot,0/6] arm: socfpga: gen5: DM improvements

Message ID 20190723202758.21295-1-simon.k.r.goldschmidt@gmail.com
Headers show
Series arm: socfpga: gen5: DM improvements | expand

Message

Simon Goldschmidt July 23, 2019, 8:27 p.m. UTC 
This series ports more ad-hoc code to DM drivers (reset, clk, timer).


Simon Goldschmidt (6):
  ddr: socfpga: gen5: constify altera_gen5_sdram_ops
  arm: socfpga: gen5: increase SPL_SYS_MALLOC_F_LEN
  timer: dw-apb: add reset handling
  arm: socfpga: gen5: move initial reset handling to reset driver
  arm: socfpga: gen5: add readonly clk driver
  arm: socfpga: gen5: use DM_TIMER for systick

 MAINTAINERS                                   |   1 +
 arch/arm/dts/socfpga-common-u-boot.dtsi       |  78 ++++
 arch/arm/dts/socfpga.dtsi                     |   5 +
 .../dts/socfpga_cyclone5_socrates-u-boot.dtsi |   1 +
 .../socfpga_cyclone5_socrates_handoff.dtsi    |  26 ++
 arch/arm/mach-socfpga/Kconfig                 |   7 +-
 arch/arm/mach-socfpga/Makefile                |   1 -
 arch/arm/mach-socfpga/reset_manager_gen5.c    |  13 -
 arch/arm/mach-socfpga/spl_gen5.c              |  24 +-
 arch/arm/mach-socfpga/timer.c                 |  23 --
 drivers/clk/altera/Makefile                   |   1 +
 drivers/clk/altera/clk-gen5.c                 | 338 ++++++++++++++++++
 drivers/ddr/altera/sdram_gen5.c               |   2 +-
 drivers/timer/dw-apb-timer.c                  |  18 +-
 14 files changed, 483 insertions(+), 55 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates_handoff.dtsi
 delete mode 100644 arch/arm/mach-socfpga/timer.c
 create mode 100644 drivers/clk/altera/clk-gen5.c

Comments

Simon Goldschmidt July 23, 2019, 8:33 p.m. UTC | #1 
Am 23.07.2019 um 22:27 schrieb Simon Goldschmidt:
> This series ports more ad-hoc code to DM drivers (reset, clk, timer).

This is how far I got with DM/DTS "conversion" for now. Converting from 
"board/qts/*.h" to DTS is still pending since I yet failed to find a 
solution that allows FPGA images to define different clock or I/O 
requirements without requiring Linux drivers for clock or pinmux...

Converting from "board/qts/*.h" to U-Boot devicetree is probably not too 
hard, but reconfiguration after configuring the FPGA (e.g. from FIT) 
requires more work.

BTW, we're now quite short on SRAM in SPL. Next steps on this platform 
might require to separate "boot from MMC" and "boot from QSPI" to reduce 
SRAM usage.

Regards,
Simon

> 
> 
> Simon Goldschmidt (6):
>    ddr: socfpga: gen5: constify altera_gen5_sdram_ops
>    arm: socfpga: gen5: increase SPL_SYS_MALLOC_F_LEN
>    timer: dw-apb: add reset handling
>    arm: socfpga: gen5: move initial reset handling to reset driver
>    arm: socfpga: gen5: add readonly clk driver
>    arm: socfpga: gen5: use DM_TIMER for systick
> 
>   MAINTAINERS                                   |   1 +
>   arch/arm/dts/socfpga-common-u-boot.dtsi       |  78 ++++
>   arch/arm/dts/socfpga.dtsi                     |   5 +
>   .../dts/socfpga_cyclone5_socrates-u-boot.dtsi |   1 +
>   .../socfpga_cyclone5_socrates_handoff.dtsi    |  26 ++
>   arch/arm/mach-socfpga/Kconfig                 |   7 +-
>   arch/arm/mach-socfpga/Makefile                |   1 -
>   arch/arm/mach-socfpga/reset_manager_gen5.c    |  13 -
>   arch/arm/mach-socfpga/spl_gen5.c              |  24 +-
>   arch/arm/mach-socfpga/timer.c                 |  23 --
>   drivers/clk/altera/Makefile                   |   1 +
>   drivers/clk/altera/clk-gen5.c                 | 338 ++++++++++++++++++
>   drivers/ddr/altera/sdram_gen5.c               |   2 +-
>   drivers/timer/dw-apb-timer.c                  |  18 +-
>   14 files changed, 483 insertions(+), 55 deletions(-)
>   create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates_handoff.dtsi
>   delete mode 100644 arch/arm/mach-socfpga/timer.c
>   create mode 100644 drivers/clk/altera/clk-gen5.c
>