diff mbox series

[20/22] hw/imc: Cleanup code to define scom addr for IMC at run time

Message ID 20210625061937.47314-21-hegdevasant@linux.vnet.ibm.com
State Accepted
Headers show
Series P9 cleanup and fixes | expand

Checks

Context Check Description
snowpatch_ozlabs/apply_patch success Successfully applied on branch master (5be38b672c1410e2f10acd3ad2eecfdc81d5daf7)
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot success Test snowpatch/job/snowpatch-skiboot on branch master
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot-dco success Signed-off-by present

Commit Message

Vasant Hegde June 25, 2021, 6:19 a.m. UTC 
From: Anju T Sudhakar <anju@linux.vnet.ibm.com>

Currently scom addresses for IMC are defined at compile time.
The scom addresses may vary for different processor generations.
So clean up the code to pick the right scom addresses, based on
the processor version at run time.

Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
---
 hw/imc.c      | 34 ++++++++++++++++++++++++++++++++--
 include/imc.h |  4 ++--
 2 files changed, 34 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/hw/imc.c b/hw/imc.c
index c186da04c..cae112041 100644
--- a/hw/imc.c
+++ b/hw/imc.c
@@ -28,6 +28,15 @@ 
 					 * b’000’- 4K entries * 64 per
 					 * entry = 256K buffersize
 					 */
+static uint64_t TRACE_IMC_ADDR;
+static uint64_t CORE_IMC_EVENT_MASK_ADDR;
+/*
+ * Initialise these with the pdbar and htm scom port address array
+ * at run time, based on the processor version.
+ */
+static unsigned int *pdbar_scom_index;
+static unsigned int *htm_scom_index;
+
 /*
  * Nest IMC PMU names along with their bit values as represented in the
  * imc_chip_avl_vector(in struct imc_chip_cb, look at include/imc.h).
@@ -142,13 +151,13 @@  static bool is_nest_mem_initialized(struct imc_chip_cb *ptr)
  * SCOM port addresses in the arrays below, each for Hardware Trace Macro (HTM)
  * mode and PDBAR.
  */
-static unsigned int pdbar_scom_index[] = {
+static unsigned int pdbar_scom_index_p9[] = {
 	0x1001220B,
 	0x1001230B,
 	0x1001260B,
 	0x1001270B
 };
-static unsigned int htm_scom_index[] = {
+static unsigned int htm_scom_index_p9[] = {
 	0x10012200,
 	0x10012300,
 	0x10012600,
@@ -530,6 +539,22 @@  void imc_decompress_catalog(void)
 	xz_start_decompress(imc_xz);
 }
 
+static int setup_imc_scoms(void)
+{
+	switch (proc_gen) {
+	case proc_gen_p9:
+		CORE_IMC_EVENT_MASK_ADDR = CORE_IMC_EVENT_MASK_ADDR_P9;
+		TRACE_IMC_ADDR = TRACE_IMC_ADDR_P9;
+		pdbar_scom_index = pdbar_scom_index_p9;
+		htm_scom_index = htm_scom_index_p9;
+		return 0;
+	default:
+		prerror("%s: Unknown cpu type\n", __func__);
+		break;
+	}
+	return -1;
+}
+
 /*
  * Load the IMC pnor partition and find the appropriate sub-partition
  * based on the platform's PVR.
@@ -624,6 +649,11 @@  imc_mambo:
 		disable_imc_type_from_dt(dev, IMC_COUNTER_CHIP);
 	}
 
+	if (setup_imc_scoms()) {
+		prerror("IMC: Failed to setup the scoms\n");
+		goto err;
+	}
+
 	/*
 	 * If the dt_attach_root() fails, "imc-counters" node will not be
 	 * seen in the device-tree and hence OS should not make any
diff --git a/include/imc.h b/include/imc.h
index 7aae7921b..a446dc581 100644
--- a/include/imc.h
+++ b/include/imc.h
@@ -109,7 +109,7 @@  struct imc_chip_cb
 /*
  * Core IMC SCOMs
  */
-#define CORE_IMC_EVENT_MASK_ADDR	0x20010AA8ull
+#define CORE_IMC_EVENT_MASK_ADDR_P9	0x20010AA8ull
 #define CORE_IMC_EVENT_MASK		0x0402010000000000ull
 #define CORE_IMC_PDBAR_MASK		0x0003ffffffffe000ull
 #define CORE_IMC_HTM_MODE_ENABLE	0xE800000000000000ull
@@ -132,7 +132,7 @@  struct imc_chip_cb
  *     		|		 |	       |
  *     		*CPMC1SEL	 *CPMC2SEL     *BUFFERSIZE
  */
-#define TRACE_IMC_ADDR            0x20010AA9ull
+#define TRACE_IMC_ADDR_P9            0x20010AA9ull
 #define TRACE_IMC_SAMPLESEL(x)	((uint64_t)x << 62)
 #define TRACE_IMC_CPMC_LOAD(x)	((0xffffffff - (uint64_t)x) << 30)
 #define TRACE_IMC_CPMC1SEL(x)	((uint64_t)x << 23)