diff mbox series

[18/22] asm/head.S: Fix early SPR inits for big core

Message ID 20210625061937.47314-19-hegdevasant@linux.vnet.ibm.com
State Accepted
Headers show
Series P9 cleanup and fixes | expand

Checks

Context Check Description
snowpatch_ozlabs/apply_patch success Successfully applied on branch master (5be38b672c1410e2f10acd3ad2eecfdc81d5daf7)
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot success Test snowpatch/job/snowpatch-skiboot on branch master
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot-dco success Signed-off-by present

Commit Message

Vasant Hegde June 25, 2021, 6:19 a.m. UTC 
From: Nicholas Piggin <npiggin@gmail.com>

Without this the shared SPRs on the secondary cores are not set.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
 asm/head.S | 34 +++++++++++++++++++++++++---------
 1 file changed, 25 insertions(+), 9 deletions(-)
diff mbox series

Patch

diff --git a/asm/head.S b/asm/head.S
index 7058f734d..d773bde04 100644
--- a/asm/head.S
+++ b/asm/head.S
@@ -380,23 +380,39 @@  boot_entry:
 #endif
 	mtmsrd	%r3,0
 
-	/* If fused, t1 is primary chiplet and must init shared sprs */
+	mfspr	%r31,SPR_PIR
+
 	andi.	%r3,%r25,1
-	beq	not_fused
+	bne	fused
 
-	mfspr	%r31,SPR_PIR
-	andi.	%r3,%r31,1
-	bnel	init_shared_sprs
+	/* Apply core-mask PIR */
+	and	%r0,%r31,%r26
 
-not_fused:
-	/* Check our PIR, avoid threads */
-	mfspr	%r31,SPR_PIR
-	and.	%r0,%r31,%r26
+	/* t0 is primary for small-core */
+	cmpdi	%r0,0
 	bne	secondary_wait
 
 	/* Initialize per-core SPRs */
 	bl	init_shared_sprs
+	b	go_primary
+
+fused:
+	/* Apply core-mask PIR */
+	ori	%r0,%r26,1	/* include both sub-cores in the core mask */
+	and	%r0,%r31,%r0
+
+	/* If fused, t0, t1 are primaries for sub-cores */
+	cmpdi	%r0,0
+	bne	1f
+	bl	init_shared_sprs
+	b	go_primary /* but only t0 can be a boot CPU */
+1:
+	cmpdi	%r0,1
+	bne	secondary_wait
+	bl	init_shared_sprs
+	b	secondary_wait
 
+go_primary:
 	/* Pick a boot CPU, cpu index in r31 */
 	LOAD_IMM32(%r3, boot_sem - __head)
 	add	%r3,%r3,%r30