| Message ID | 20240321100422.5347-8-saif.abrar@linux.vnet.ibm.com |
|---|---|
| State | New |
| Headers | show |
| Series | pnv/phb4: Update PHB4 to the latest spec PH5 | expand |
On 3/21/24 11:04, Saif Abrar wrote: > Get the current link-status from PCIE macro. > Extract link-speed and link-width from the link-status > and set in the DLP training control (PCIE_DLP_TCR) register. > > Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > hw/pci-host/pnv_phb4.c | 21 +++++++++++++++++++-- > 1 file changed, 19 insertions(+), 2 deletions(-) > > diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c > index 7b3d75bae6..6823ffab54 100644 > --- a/hw/pci-host/pnv_phb4.c > +++ b/hw/pci-host/pnv_phb4.c > @@ -980,10 +980,27 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) > val |= PHB_PCIE_SCR_PLW_X16; /* RO bit */ > break; > > - /* Link training always appears trained */ > case PHB_PCIE_DLP_TRAIN_CTL: > - /* TODO: Do something sensible with speed ? */ > + /* Link training always appears trained */ > val |= PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT; > + > + /* Get the current link-status from PCIE */ > + uint32_t exp_offset = get_exp_offset(phb); > + uint32_t lnkstatus = bswap32(pnv_phb4_rc_config_read(phb, > + exp_offset + PCI_EXP_LNKSTA, 4)); > + > + /* Extract link-speed from the link-status */ > + uint32_t v = lnkstatus & PCI_EXP_LNKSTA_CLS; > + /* Set the current link-speed at the LINK_SPEED position */ > + val = SETFIELD(PHB_PCIE_DLP_LINK_SPEED, val, v); > + > + /* > + * Extract link-width from the link-status, > + * after shifting the required bitfields. > + */ > + v = (lnkstatus & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; > + /* Set the current link-width at the LINK_WIDTH position */ > + val = SETFIELD(PHB_PCIE_DLP_LINK_WIDTH, val, v); > return val; > > /*
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 7b3d75bae6..6823ffab54 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -980,10 +980,27 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) val |= PHB_PCIE_SCR_PLW_X16; /* RO bit */ break; - /* Link training always appears trained */ case PHB_PCIE_DLP_TRAIN_CTL: - /* TODO: Do something sensible with speed ? */ + /* Link training always appears trained */ val |= PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT; + + /* Get the current link-status from PCIE */ + uint32_t exp_offset = get_exp_offset(phb); + uint32_t lnkstatus = bswap32(pnv_phb4_rc_config_read(phb, + exp_offset + PCI_EXP_LNKSTA, 4)); + + /* Extract link-speed from the link-status */ + uint32_t v = lnkstatus & PCI_EXP_LNKSTA_CLS; + /* Set the current link-speed at the LINK_SPEED position */ + val = SETFIELD(PHB_PCIE_DLP_LINK_SPEED, val, v); + + /* + * Extract link-width from the link-status, + * after shifting the required bitfields. + */ + v = (lnkstatus & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; + /* Set the current link-width at the LINK_WIDTH position */ + val = SETFIELD(PHB_PCIE_DLP_LINK_WIDTH, val, v); return val; /*
Get the current link-status from PCIE macro. Extract link-speed and link-width from the link-status and set in the DLP training control (PCIE_DLP_TCR) register. Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com> --- hw/pci-host/pnv_phb4.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-)