From patchwork Thu Mar 21 10:04:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Saif Abrar X-Patchwork-Id: 1914348 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=IFl9waxz; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4V0h2G6bFDz1yWy for ; Thu, 21 Mar 2024 21:06:46 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnFIx-0007bX-EM; Thu, 21 Mar 2024 06:05:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFIH-00072I-Cj; Thu, 21 Mar 2024 06:05:08 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFI1-0007Yu-FD; Thu, 21 Mar 2024 06:05:04 -0400 Received: from pps.filterd (m0353728.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 42L9tmjd032392; Thu, 21 Mar 2024 10:04:38 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=g8ymaAhhz8mBn3W1p/yjiLJCu2ruL9drdKnC6kGOb7s=; b=IFl9waxzwW406mVpgcbvh82eIlwo21MxSKBBEvzIkkXlPooxwv02PeWsZoPEpYIKXLwd Z8bR18L8IXu9ZonYGMMA6GscpFjegDNPFKxIXTMpZifvsvsvwq98vFW1b7H1j1VRLcEf jrneFbLOMXt7sofZWszpOVvVbNn/7OyPcuAGqkjd0tver7HlCGetE5D3I3zESOlx6X7I FZAtjYK/I2Ej8DZ1IwOxPQPotkTaYIoFh/lUf8N4vlr44yVK3vCkY2u+6Y6aIUTlWZ9P /jlsPwU+BDiuFe4VpluYPTQwAVa4RIJSqiYwavbjmhRIE9IszYR8aVLs4T4fsmEyhqxE Gw== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0gta09d4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:38 +0000 Received: from m0353728.ppops.net (m0353728.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 42LA4bUZ019710; Thu, 21 Mar 2024 10:04:37 GMT Received: from ppma13.dal12v.mail.ibm.com (dd.9e.1632.ip4.static.sl-reverse.com [50.22.158.221]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0gta09d2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:37 +0000 Received: from pps.filterd (ppma13.dal12v.mail.ibm.com [127.0.0.1]) by ppma13.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 42L7OV9Q019878; Thu, 21 Mar 2024 10:04:36 GMT Received: from smtprelay05.dal12v.mail.ibm.com ([172.16.1.7]) by ppma13.dal12v.mail.ibm.com (PPS) with ESMTPS id 3wwqykv0p3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:36 +0000 Received: from smtpav04.dal12v.mail.ibm.com (smtpav04.dal12v.mail.ibm.com [10.241.53.103]) by smtprelay05.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 42LA4Yt347448320 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 21 Mar 2024 10:04:36 GMT Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0D6A758062; Thu, 21 Mar 2024 10:04:34 +0000 (GMT) Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8E1C85805A; Thu, 21 Mar 2024 10:04:33 +0000 (GMT) Received: from gfwr516.rchland.ibm.com (unknown [9.10.239.105]) by smtpav04.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 21 Mar 2024 10:04:33 +0000 (GMT) From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH 01/10] qtest/phb4: Add testbench for PHB4 Date: Thu, 21 Mar 2024 05:04:13 -0500 Message-Id: <20240321100422.5347-2-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> References: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: XlclDVvXX1rPE9gpz4Jkfqza7cB_ah4C X-Proofpoint-GUID: HRBOU0qF6-YPLCQZUKJ694SFpk-jnYqx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-21_06,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 phishscore=0 bulkscore=0 mlxlogscore=795 spamscore=0 clxscore=1015 suspectscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2403140000 definitions=main-2403210069 Received-SPF: none client-ip=148.163.156.1; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org New qtest TB added for PHB4. TB reads PHB Version register and asserts that bits[24:31] have value 0xA5. Signed-off-by: Saif Abrar --- tests/qtest/meson.build | 1 + tests/qtest/pnv-phb4-test.c | 74 +++++++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 tests/qtest/pnv-phb4-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 36c5c13a7b..4795e51c17 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -168,6 +168,7 @@ qtests_ppc64 = \ (config_all_devices.has_key('CONFIG_PSERIES') ? ['device-plug-test'] : []) + \ (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-xscom-test'] : []) + \ (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-host-i2c-test'] : []) + \ + (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-phb4-test'] : []) + \ (config_all_devices.has_key('CONFIG_PSERIES') ? ['rtas-test'] : []) + \ (slirp.found() ? ['pxe-test'] : []) + \ (config_all_devices.has_key('CONFIG_USB_UHCI') ? ['usb-hcd-uhci-test'] : []) + \ diff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c new file mode 100644 index 0000000000..e3b809e9c4 --- /dev/null +++ b/tests/qtest/pnv-phb4-test.c @@ -0,0 +1,74 @@ +/* + * QTest testcase for PowerNV PHB4 + * + * Copyright (c) 2024, IBM Corporation. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "hw/pci-host/pnv_phb4_regs.h" + +#define P10_XSCOM_BASE 0x000603fc00000000ull +#define PHB4_MMIO 0x000600c3c0000000ull +#define PHB4_XSCOM 0x8010900ull + +#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) +#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) + +static uint64_t pnv_xscom_addr(uint32_t pcba) +{ + return P10_XSCOM_BASE | ((uint64_t) pcba << 3); +} + +static uint64_t pnv_phb4_xscom_addr(uint32_t reg) +{ + return pnv_xscom_addr(PHB4_XSCOM + reg); +} + +/* + * XSCOM read/write is indirect in PHB4: + * Write 'SCOM - HV Indirect Address Register' + * with register-offset to read/write. + - bit[0]: Valid Bit + - bit[51:61]: Indirect Address(00:10) + * Read/write 'SCOM - HV Indirect Data Register' to get/set the value. + */ + +static uint64_t pnv_phb4_xscom_read(QTestState *qts, uint32_t reg) +{ + qtest_writeq(qts, pnv_phb4_xscom_addr(PHB_SCOM_HV_IND_ADDR), + PPC_BIT(0) | reg); + return qtest_readq(qts, pnv_phb4_xscom_addr(PHB_SCOM_HV_IND_DATA)); +} + +/* Assert that 'PHB - Version Register Offset 0x0800' bits-[24:31] are 0xA5 */ +static void phb4_version_test(QTestState *qts) +{ + uint64_t ver = pnv_phb4_xscom_read(qts, PHB_VERSION); + + /* PHB Version register [24:31]: Major Revision ID 0xA5 */ + ver = ver >> (63 - 31); + g_assert_cmpuint(ver, ==, 0xA5); +} + +static void test_phb4(void) +{ + QTestState *qts = NULL; + + qts = qtest_initf("-machine powernv10 -accel tcg -nographic -d unimp"); + + /* Make sure test is running on PHB */ + phb4_version_test(qts); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + qtest_add_func("phb4", test_phb4); + return g_test_run(); +} From patchwork Thu Mar 21 10:04:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Saif Abrar X-Patchwork-Id: 1914345 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=fKmQgZTM; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4V0h270tHTz1yWy for ; Thu, 21 Mar 2024 21:06:39 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnFIx-0007bB-DU; Thu, 21 Mar 2024 06:05:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFI8-000706-6w; Thu, 21 Mar 2024 06:04:56 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFI4-0007Z6-L0; Thu, 21 Mar 2024 06:04:54 -0400 Received: from pps.filterd (m0353729.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 42L8UEIB031704; Thu, 21 Mar 2024 10:04:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=YnasUjAzqJPULha4qOGtagAtf5QI/CkXuLQkGj0RKoM=; b=fKmQgZTMWSIoNwThzkCVdFAK/7V2YsileaF7RkDGWu9LxzQIEMT0FW5S/H8eGvOeI5JI CxnxbqIBBT5BWM2bha3j3w4jD8eFqtscILjgUcgY7x7pmrYrcp5MzzSzpjEqCPZvw0A7 kZlzYoADsbWr5pgLw4cmsM3vHduendG5KR2qExIKMwd4ZpDyAP+I2xoDqNjqPvGhlf+5 fCL4P4ci2y8kxU+CfJxLt/zvxsIaXCvOCTrAkd9N9IXJLbJHAGjiey5zG5BtKwJ+gS2J cMhtFDD8H/tSMTaqkFMYuKe3VLwZukOsYNLZLjcQeN5tXKrD8IgUpOyPAW+m5IFf+Yhm Uw== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0c6m0usv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:39 +0000 Received: from m0353729.ppops.net (m0353729.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 42LA4dMF010226; Thu, 21 Mar 2024 10:04:39 GMT Received: from ppma22.wdc07v.mail.ibm.com (5c.69.3da9.ip4.static.sl-reverse.com [169.61.105.92]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0c6m0ust-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:38 +0000 Received: from pps.filterd (ppma22.wdc07v.mail.ibm.com [127.0.0.1]) by ppma22.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 42L8qiHs015792; Thu, 21 Mar 2024 10:04:37 GMT Received: from smtprelay05.dal12v.mail.ibm.com ([172.16.1.7]) by ppma22.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3wwp50cfk2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:37 +0000 Received: from smtpav04.dal12v.mail.ibm.com (smtpav04.dal12v.mail.ibm.com [10.241.53.103]) by smtprelay05.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 42LA4YhN24117884 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 21 Mar 2024 10:04:36 GMT Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 918BC58052; Thu, 21 Mar 2024 10:04:34 +0000 (GMT) Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1B7DA58066; Thu, 21 Mar 2024 10:04:34 +0000 (GMT) Received: from gfwr516.rchland.ibm.com (unknown [9.10.239.105]) by smtpav04.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 21 Mar 2024 10:04:34 +0000 (GMT) From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH 02/10] pnv/phb4: Add reset logic to PHB4 Date: Thu, 21 Mar 2024 05:04:14 -0500 Message-Id: <20240321100422.5347-3-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> References: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: jhlvPbyKxV8dXqlJjNEJT-qTweMeVf9D X-Proofpoint-ORIG-GUID: PEfD5w5s1m_VRrqYtOrmY7iN3V-s4u9W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-21_06,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 spamscore=0 impostorscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 mlxscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2403140000 definitions=main-2403210069 Received-SPF: none client-ip=148.163.156.1; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add a method to be invoked on QEMU reset. Also add CFG and PBL core-blocks reset logic using appropriate bits of PHB_PCIE_CRESET register. Tested by reading the reset value of a register. Signed-off-by: Saif Abrar --- hw/pci-host/pnv_phb4.c | 104 +++++++++++++++++++++++++++- include/hw/pci-host/pnv_phb4_regs.h | 16 ++++- tests/qtest/pnv-phb4-test.c | 10 +++ 3 files changed, 127 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 075499d36d..d2e7403b37 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1,7 +1,7 @@ /* - * QEMU PowerPC PowerNV (POWER9) PHB4 model + * QEMU PowerPC PowerNV (POWER10) PHB4 model * - * Copyright (c) 2018-2020, IBM Corporation. + * Copyright (c) 2018-2024, IBM Corporation. * * This code is licensed under the GPL version 2 or later. See the * COPYING file in the top-level directory. @@ -22,6 +22,7 @@ #include "hw/qdev-properties.h" #include "qom/object.h" #include "trace.h" +#include "sysemu/reset.h" #define phb_error(phb, fmt, ...) \ qemu_log_mask(LOG_GUEST_ERROR, "phb4[%d:%d]: " fmt "\n", \ @@ -499,6 +500,86 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb) } } +/* + * Get the PCI-E capability offset from the root-port + */ +static uint32_t get_exp_offset(PnvPHB4 *phb) +{ + PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); + PCIDevice *pdev; + pdev = pci_find_device(pci->bus, 0, 0); + if (!pdev) { + phb_error(phb, "PCI device not found"); + return ~0; + } + PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(pdev); + return rpc->exp_offset; +} + +#define RC_CONFIG_WRITE(a, v) pnv_phb4_rc_config_write(phb, a, 4, v); + +static void pnv_phb4_cfg_core_reset(PnvPHB4 *phb) +{ + /* Zero all registers initially */ + int i; + for (i = PCI_COMMAND ; i < PHB_RC_CONFIG_SIZE ; i += 4) { + RC_CONFIG_WRITE(i, 0) + } + + RC_CONFIG_WRITE(PCI_COMMAND, 0x100100); + RC_CONFIG_WRITE(PCI_CLASS_REVISION, 0x6040000); + RC_CONFIG_WRITE(PCI_CACHE_LINE_SIZE, 0x10000); + RC_CONFIG_WRITE(PCI_MEMORY_BASE, 0x10); + RC_CONFIG_WRITE(PCI_PREF_MEMORY_BASE, 0x10011); + RC_CONFIG_WRITE(PCI_CAPABILITY_LIST, 0x40); + RC_CONFIG_WRITE(PCI_INTERRUPT_LINE, 0x20000); + /* PM Capabilities Register */ + RC_CONFIG_WRITE(PCI_BRIDGE_CONTROL + PCI_PM_PMC, 0xC8034801); + + uint32_t exp_offset = get_exp_offset(phb); + RC_CONFIG_WRITE(exp_offset, 0x420010); + RC_CONFIG_WRITE(exp_offset + PCI_EXP_DEVCAP, 0x8022); + RC_CONFIG_WRITE(exp_offset + PCI_EXP_DEVCTL, 0x140); + RC_CONFIG_WRITE(exp_offset + PCI_EXP_LNKCAP, 0x300105); + RC_CONFIG_WRITE(exp_offset + PCI_EXP_LNKCTL, 0x2010008); + RC_CONFIG_WRITE(exp_offset + PCI_EXP_SLTCTL, 0x2000); + RC_CONFIG_WRITE(exp_offset + PCI_EXP_DEVCAP2, 0x1003F); + RC_CONFIG_WRITE(exp_offset + PCI_EXP_DEVCTL2, 0x20); + RC_CONFIG_WRITE(exp_offset + PCI_EXP_LNKCAP2, 0x80003E); + RC_CONFIG_WRITE(exp_offset + PCI_EXP_LNKCTL2, 0x5); + + RC_CONFIG_WRITE(PHB_AER_ECAP, 0x14810001); + RC_CONFIG_WRITE(PHB_AER_CAPCTRL, 0xA0); + RC_CONFIG_WRITE(PHB_SEC_ECAP, 0x1A010019); + + RC_CONFIG_WRITE(PHB_LMR_ECAP, 0x1E810027); + /* LMR - Margining Lane Control / Status Register # 2 to 16 */ + for (i = PHB_LMR_CTLSTA_2 ; i <= PHB_LMR_CTLSTA_16 ; i += 4) { + RC_CONFIG_WRITE(i, 0x9C38); + } + + RC_CONFIG_WRITE(PHB_DLF_ECAP, 0x1F410025); + RC_CONFIG_WRITE(PHB_DLF_CAP, 0x80000001); + RC_CONFIG_WRITE(P16_ECAP, 0x22410026); + RC_CONFIG_WRITE(P32_ECAP, 0x1002A); + RC_CONFIG_WRITE(P32_CAP, 0x103); +} + +static void pnv_phb4_pbl_core_reset(PnvPHB4 *phb) +{ + /* Zero all registers initially */ + int i; + for (i = PHB_PBL_CONTROL ; i <= PHB_PBL_ERR1_STATUS_MASK ; i += 8) { + phb->regs[i >> 3] = 0x0; + } + + /* Set specific register values */ + phb->regs[PHB_PBL_CONTROL >> 3] = 0xC009000000000000; + phb->regs[PHB_PBL_TIMEOUT_CTRL >> 3] = 0x2020000000000000; + phb->regs[PHB_PBL_NPTAG_ENABLE >> 3] = 0xFFFFFFFF00000000; + phb->regs[PHB_PBL_SYS_LINK_INIT >> 3] = 0x80088B4642473000; +} + static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size) { @@ -612,6 +693,16 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, pnv_phb4_update_xsrc(phb); break; + /* Reset core blocks */ + case PHB_PCIE_CRESET: + if (val & PHB_PCIE_CRESET_CFG_CORE) { + pnv_phb4_cfg_core_reset(phb); + } + if (val & PHB_PCIE_CRESET_PBL) { + pnv_phb4_pbl_core_reset(phb); + } + break; + /* Silent simple writes */ case PHB_ASN_CMPM: case PHB_CONFIG_ADDRESS: @@ -1531,6 +1622,13 @@ static void pnv_phb4_xscom_realize(PnvPHB4 *phb) static PCIIOMMUOps pnv_phb4_iommu_ops = { .get_address_space = pnv_phb4_dma_iommu, }; +static void pnv_phb4_reset(void *dev) +{ + PnvPHB4 *phb = PNV_PHB4(dev); + pnv_phb4_cfg_core_reset(phb); + pnv_phb4_pbl_core_reset(phb); + phb->regs[PHB_PCIE_CRESET >> 3] = 0xE000000000000000; +} static void pnv_phb4_instance_init(Object *obj) { @@ -1608,6 +1706,8 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp) phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs); pnv_phb4_xscom_realize(phb); + + qemu_register_reset(pnv_phb4_reset, dev); } /* diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_phb4_regs.h index bea96f4d91..6892e21cc9 100644 --- a/include/hw/pci-host/pnv_phb4_regs.h +++ b/include/hw/pci-host/pnv_phb4_regs.h @@ -343,6 +343,18 @@ #define PHB_RC_CONFIG_BASE 0x1000 #define PHB_RC_CONFIG_SIZE 0x800 +#define PHB_AER_ECAP 0x100 +#define PHB_AER_CAPCTRL 0x118 +#define PHB_SEC_ECAP 0x148 +#define PHB_LMR_ECAP 0x1A0 +#define PHB_LMR_CTLSTA_2 0x1AC +#define PHB_LMR_CTLSTA_16 0x1E4 +#define PHB_DLF_ECAP 0x1E8 +#define PHB_DLF_CAP 0x1EC +#define P16_ECAP 0x1F4 +#define P32_ECAP 0x224 +#define P32_CAP 0x228 + /* PHB4 REGB registers */ /* PBL core */ @@ -368,7 +380,7 @@ #define PHB_PCIE_SCR 0x1A00 #define PHB_PCIE_SCR_SLOT_CAP PPC_BIT(15) #define PHB_PCIE_SCR_MAXLINKSPEED PPC_BITMASK(32, 35) - +#define PHB_PCIE_BNR 0x1A08 #define PHB_PCIE_CRESET 0x1A10 #define PHB_PCIE_CRESET_CFG_CORE PPC_BIT(0) @@ -423,6 +435,8 @@ #define PHB_PCIE_LANE_EQ_CNTL23 0x1B08 /* DD1 only */ #define PHB_PCIE_TRACE_CTRL 0x1B20 #define PHB_PCIE_MISC_STRAP 0x1B30 +#define PHB_PCIE_PHY_RXEQ_STAT_G3_00_03 0x1B40 +#define PHB_PCIE_PHY_RXEQ_STAT_G5_12_15 0x1B98 /* Error */ #define PHB_REGB_ERR_STATUS 0x1C00 diff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c index e3b809e9c4..44141462f6 100644 --- a/tests/qtest/pnv-phb4-test.c +++ b/tests/qtest/pnv-phb4-test.c @@ -54,6 +54,13 @@ static void phb4_version_test(QTestState *qts) g_assert_cmpuint(ver, ==, 0xA5); } +/* Assert that 'PHB PBL Control' register has correct reset value */ +static void phb4_reset_test(QTestState *qts) +{ + g_assert_cmpuint(pnv_phb4_xscom_read(qts, PHB_PBL_CONTROL), + ==, 0xC009000000000000); +} + static void test_phb4(void) { QTestState *qts = NULL; @@ -63,6 +70,9 @@ static void test_phb4(void) /* Make sure test is running on PHB */ phb4_version_test(qts); + /* Check reset value of a register */ + phb4_reset_test(qts); + qtest_quit(qts); } From patchwork Thu Mar 21 10:04:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Saif Abrar X-Patchwork-Id: 1914340 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=nNaA7GB0; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4V0h1D0bRfz23rR for ; Thu, 21 Mar 2024 21:05:52 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnFIr-0007Wq-Ol; Thu, 21 Mar 2024 06:05:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFI8-000707-8A; Thu, 21 Mar 2024 06:04:56 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFI5-0007Z3-RW; Thu, 21 Mar 2024 06:04:55 -0400 Received: from pps.filterd (m0356517.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 42L6sCg0023936; Thu, 21 Mar 2024 10:04:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=8zraPkvW4ET16KSAnHl1dIdf5lqFjbzuP06NPy2jmzY=; b=nNaA7GB05hdjiFEPCDm94Wfnv4zQZmPLSXYTto5IVvh7fTWqJuumy/POcYMfkfX3Of3y 92i5ZfqLuoq7LpSIWLjontw8VDBZUJn0ktovKoNMuCS8HLvxGnQ9Nw4p0E7noEF4SzB9 Y4JT9P+O/gZt8wNw+H5TMxXISNshOxhJi18LSyjPGjJPUlNaooS8voqeefL8C+twHW8c zfIh5Mm+lWnXnYgWTVVFOhDdH8KxpLQN+XACwRQaS7ZRqPBei6qz3NpBCnYnIhFMGBIX DVE7R/Tjq3OIDV3F1mVadG09G3VAh/Zgr8MQTDOwc1xbDjWujalEmtgQq9c84YUHSXRu Zg== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0e5ugmb6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:39 +0000 Received: from m0356517.ppops.net (m0356517.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 42LA44Ml020257; Thu, 21 Mar 2024 10:04:39 GMT Received: from ppma12.dal12v.mail.ibm.com (dc.9e.1632.ip4.static.sl-reverse.com [50.22.158.220]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0e5ugmb5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:38 +0000 Received: from pps.filterd (ppma12.dal12v.mail.ibm.com [127.0.0.1]) by ppma12.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 42L91V94017190; Thu, 21 Mar 2024 10:04:38 GMT Received: from smtprelay02.dal12v.mail.ibm.com ([172.16.1.4]) by ppma12.dal12v.mail.ibm.com (PPS) with ESMTPS id 3wwnrtmh7k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:38 +0000 Received: from smtpav04.dal12v.mail.ibm.com (smtpav04.dal12v.mail.ibm.com [10.241.53.103]) by smtprelay02.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 42LA4ZM146727592 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 21 Mar 2024 10:04:37 GMT Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2132A58064; Thu, 21 Mar 2024 10:04:35 +0000 (GMT) Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9F67C5805A; Thu, 21 Mar 2024 10:04:34 +0000 (GMT) Received: from gfwr516.rchland.ibm.com (unknown [9.10.239.105]) by smtpav04.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 21 Mar 2024 10:04:34 +0000 (GMT) From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH 03/10] pnv/phb4: Implement sticky reset logic in PHB4 Date: Thu, 21 Mar 2024 05:04:15 -0500 Message-Id: <20240321100422.5347-4-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> References: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: gHUN7C87n3BWnK4jk3zDtHvmL--g585X X-Proofpoint-GUID: loFHIl9QBMMER0DQvImF9Y_m3oyht9ur X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-21_06,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2403140000 definitions=main-2403210069 Received-SPF: none client-ip=148.163.156.1; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sticky bits retain their values on reset and are not overwritten with the reset value. Added sticky reset logic for all required registers, i.e. CFG core, PBL core, PHB error registers, PCIE stack registers and REGB error registers. Tested by writing all 1's to the reg PHB_PBL_ERR_INJECT. This will set the bits in the reg PHB_PBL_ERR_STATUS. Reset the PBL core by setting PHB_PCIE_CRESET_PBL in reg PHB_PCIE_CRESET. Verify that the sticky bits in the PHB_PBL_ERR_STATUS reg are still set. Signed-off-by: Saif Abrar --- hw/pci-host/pnv_phb4.c | 156 ++++++++++++++++++++++++++-- include/hw/pci-host/pnv_phb4_regs.h | 20 +++- tests/qtest/pnv-phb4-test.c | 30 +++++- 3 files changed, 196 insertions(+), 10 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index d2e7403b37..b3a83837f8 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -516,14 +516,52 @@ static uint32_t get_exp_offset(PnvPHB4 *phb) return rpc->exp_offset; } -#define RC_CONFIG_WRITE(a, v) pnv_phb4_rc_config_write(phb, a, 4, v); +#define RC_CONFIG_WRITE(a, v) pnv_phb4_rc_config_write(phb, a, 4, v) + +/* + * Apply sticky-mask 's' to the reset-value 'v' and write to the address 'a'. + * RC-config space values and masks are LE. + * Method pnv_phb4_rc_config_read() returns BE, hence convert to LE. + * Compute new value in LE domain. + * New value computation using sticky-mask is in LE. + * Convert the computed value from LE to BE before writing back. + */ +#define RC_CONFIG_STICKY_RESET(a, v, s) \ + (RC_CONFIG_WRITE(a, bswap32( \ + (bswap32(pnv_phb4_rc_config_read(phb, a, 4)) & s) \ + | (v & ~s) \ + ))) static void pnv_phb4_cfg_core_reset(PnvPHB4 *phb) { - /* Zero all registers initially */ + /* + * Zero all registers initially, + * except those that have sticky reset. + */ int i; for (i = PCI_COMMAND ; i < PHB_RC_CONFIG_SIZE ; i += 4) { - RC_CONFIG_WRITE(i, 0) + switch (i) { + case PCI_EXP_LNKCTL2: + case PHB_AER_UERR: + case PHB_AER_UERR_MASK: + case PHB_AER_CERR: + case PHB_AER_CAPCTRL: + case PHB_AER_HLOG_1: + case PHB_AER_HLOG_2: + case PHB_AER_HLOG_3: + case PHB_AER_HLOG_4: + case PHB_AER_RERR: + case PHB_AER_ESID: + case PHB_DLF_STAT: + case P16_STAT: + case P16_LDPM: + case P16_FRDPM: + case P16_SRDPM: + case P32_CTL: + break; + default: + RC_CONFIG_WRITE(i, 0); + } } RC_CONFIG_WRITE(PCI_COMMAND, 0x100100); @@ -563,15 +601,55 @@ static void pnv_phb4_cfg_core_reset(PnvPHB4 *phb) RC_CONFIG_WRITE(P16_ECAP, 0x22410026); RC_CONFIG_WRITE(P32_ECAP, 0x1002A); RC_CONFIG_WRITE(P32_CAP, 0x103); + + /* Sticky reset */ + RC_CONFIG_STICKY_RESET(exp_offset + PCI_EXP_LNKCTL2, 0x5, 0xFEFFBF); + RC_CONFIG_STICKY_RESET(PHB_AER_UERR, 0, 0x1FF030); + RC_CONFIG_STICKY_RESET(PHB_AER_UERR_MASK, 0, 0x1FF030); + RC_CONFIG_STICKY_RESET(PHB_AER_CERR, 0, 0x11C1); + RC_CONFIG_STICKY_RESET(PHB_AER_CAPCTRL, 0xA0, 0x15F); + RC_CONFIG_STICKY_RESET(PHB_AER_HLOG_1, 0, 0xFFFFFFFF); + RC_CONFIG_STICKY_RESET(PHB_AER_HLOG_2, 0, 0xFFFFFFFF); + RC_CONFIG_STICKY_RESET(PHB_AER_HLOG_3, 0, 0xFFFFFFFF); + RC_CONFIG_STICKY_RESET(PHB_AER_HLOG_4, 0, 0xFFFFFFFF); + RC_CONFIG_STICKY_RESET(PHB_AER_RERR, 0, 0x7F); + RC_CONFIG_STICKY_RESET(PHB_AER_ESID, 0, 0xFFFFFFFF); + RC_CONFIG_STICKY_RESET(PHB_DLF_STAT, 0, 0x807FFFFF); + RC_CONFIG_STICKY_RESET(P16_STAT, 0, 0x1F); + RC_CONFIG_STICKY_RESET(P16_LDPM, 0, 0xFFFF); + RC_CONFIG_STICKY_RESET(P16_FRDPM, 0, 0xFFFF); + RC_CONFIG_STICKY_RESET(P16_SRDPM, 0, 0xFFFF); + RC_CONFIG_STICKY_RESET(P32_CTL, 0, 0x3); } +/* Apply sticky-mask to the reset-value and write to the reg-address */ +#define STICKY_RST(addr, rst_val, sticky_mask) (phb->regs[addr >> 3] = \ + ((phb->regs[addr >> 3] & sticky_mask) | (rst_val & ~sticky_mask))) + static void pnv_phb4_pbl_core_reset(PnvPHB4 *phb) { - /* Zero all registers initially */ + /* + * Zero all registers initially, + * with sticky reset of certain registers. + */ int i; for (i = PHB_PBL_CONTROL ; i <= PHB_PBL_ERR1_STATUS_MASK ; i += 8) { - phb->regs[i >> 3] = 0x0; + switch (i) { + case PHB_PBL_ERR_STATUS: + break; + case PHB_PBL_ERR1_STATUS: + case PHB_PBL_ERR_LOG_0: + case PHB_PBL_ERR_LOG_1: + case PHB_PBL_ERR_STATUS_MASK: + case PHB_PBL_ERR1_STATUS_MASK: + STICKY_RST(i, 0, PPC_BITMASK(0, 63)); + break; + default: + phb->regs[i >> 3] = 0x0; + } } + STICKY_RST(PHB_PBL_ERR_STATUS, 0, \ + (PPC_BITMASK(0, 9) | PPC_BITMASK(12, 63))); /* Set specific register values */ phb->regs[PHB_PBL_CONTROL >> 3] = 0xC009000000000000; @@ -703,6 +781,17 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, } break; + /* + * Writing bits to a 1 in this register will inject the error corresponding + * to the bit that is written. The bits will automatically clear to 0 after + * the error is injected. The corresponding bit in the Error Status Reg + * should also be set automatically when the error occurs. + */ + case PHB_PBL_ERR_INJECT: + phb->regs[PHB_PBL_ERR_STATUS >> 3] = phb->regs[off >> 3]; + phb->regs[off >> 3] = 0; + break; + /* Silent simple writes */ case PHB_ASN_CMPM: case PHB_CONFIG_ADDRESS: @@ -1622,12 +1711,67 @@ static void pnv_phb4_xscom_realize(PnvPHB4 *phb) static PCIIOMMUOps pnv_phb4_iommu_ops = { .get_address_space = pnv_phb4_dma_iommu, }; + +static void pnv_phb4_err_reg_reset(PnvPHB4 *phb) +{ + STICKY_RST(PHB_ERR_STATUS, 0, PPC_BITMASK(0, 33)); + STICKY_RST(PHB_ERR1_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_ERR_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_ERR1_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + + STICKY_RST(PHB_TXE_ERR_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_TXE_ERR1_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_TXE_ERR_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_TXE_ERR1_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + + STICKY_RST(PHB_RXE_ARB_ERR_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_ARB_ERR1_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_ARB_ERR_LOG_0, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_ARB_ERR_LOG_1, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_ARB_ERR_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_ARB_ERR1_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + + STICKY_RST(PHB_RXE_MRG_ERR_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_MRG_ERR1_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_MRG_ERR_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_MRG_ERR1_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + + STICKY_RST(PHB_RXE_TCE_ERR_STATUS, 0, PPC_BITMASK(0, 35)); + STICKY_RST(PHB_RXE_TCE_ERR1_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_TCE_ERR_LOG_0, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_TCE_ERR_LOG_1, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_TCE_ERR_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_TCE_ERR1_STATUS_MASK, 0, PPC_BITMASK(0, 63)); +} + +static void pnv_phb4_pcie_stack_reg_reset(PnvPHB4 *phb) +{ + STICKY_RST(PHB_PCIE_CRESET, 0xE000000000000000, \ + (PHB_PCIE_CRESET_PERST_N | PHB_PCIE_CRESET_REFCLK_N)); + STICKY_RST(PHB_PCIE_DLP_ERRLOG1, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_PCIE_DLP_ERRLOG2, 0, PPC_BITMASK(0, 31)); + STICKY_RST(PHB_PCIE_DLP_ERR_STATUS, 0, PPC_BITMASK(0, 15)); +} + +static void pnv_phb4_regb_err_reg_reset(PnvPHB4 *phb) +{ + STICKY_RST(PHB_REGB_ERR_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_REGB_ERR1_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_REGB_ERR_LOG_0, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_REGB_ERR_LOG_1, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_REGB_ERR_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_REGB_ERR1_STATUS_MASK, 0, PPC_BITMASK(0, 63)); +} + static void pnv_phb4_reset(void *dev) { PnvPHB4 *phb = PNV_PHB4(dev); pnv_phb4_cfg_core_reset(phb); pnv_phb4_pbl_core_reset(phb); - phb->regs[PHB_PCIE_CRESET >> 3] = 0xE000000000000000; + + pnv_phb4_err_reg_reset(phb); + pnv_phb4_pcie_stack_reg_reset(phb); + pnv_phb4_regb_err_reg_reset(phb); } static void pnv_phb4_instance_init(Object *obj) diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_phb4_regs.h index 6892e21cc9..df5e86d29a 100644 --- a/include/hw/pci-host/pnv_phb4_regs.h +++ b/include/hw/pci-host/pnv_phb4_regs.h @@ -344,17 +344,32 @@ #define PHB_RC_CONFIG_SIZE 0x800 #define PHB_AER_ECAP 0x100 +#define PHB_AER_UERR 0x104 +#define PHB_AER_UERR_MASK 0x108 +#define PHB_AER_CERR 0x110 #define PHB_AER_CAPCTRL 0x118 +#define PHB_AER_HLOG_1 0x11C +#define PHB_AER_HLOG_2 0x120 +#define PHB_AER_HLOG_3 0x124 +#define PHB_AER_HLOG_4 0x128 +#define PHB_AER_RERR 0x130 +#define PHB_AER_ESID 0x134 #define PHB_SEC_ECAP 0x148 #define PHB_LMR_ECAP 0x1A0 #define PHB_LMR_CTLSTA_2 0x1AC #define PHB_LMR_CTLSTA_16 0x1E4 #define PHB_DLF_ECAP 0x1E8 #define PHB_DLF_CAP 0x1EC +#define PHB_DLF_STAT 0x1F0 #define P16_ECAP 0x1F4 +#define P16_STAT 0x200 +#define P16_LDPM 0x204 +#define P16_FRDPM 0x208 +#define P16_SRDPM 0x20C #define P32_ECAP 0x224 #define P32_CAP 0x228 - +#define P32_CTL 0x22C +#define P32_STAT 0x230 /* PHB4 REGB registers */ /* PBL core */ @@ -388,8 +403,7 @@ #define PHB_PCIE_CRESET_PBL PPC_BIT(2) #define PHB_PCIE_CRESET_PERST_N PPC_BIT(3) #define PHB_PCIE_CRESET_PIPE_N PPC_BIT(4) - - +#define PHB_PCIE_CRESET_REFCLK_N PPC_BIT(8) #define PHB_PCIE_HOTPLUG_STATUS 0x1A20 #define PHB_PCIE_HPSTAT_PRESENCE PPC_BIT(10) diff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c index 44141462f6..708df3867c 100644 --- a/tests/qtest/pnv-phb4-test.c +++ b/tests/qtest/pnv-phb4-test.c @@ -36,7 +36,12 @@ static uint64_t pnv_phb4_xscom_addr(uint32_t reg) - bit[51:61]: Indirect Address(00:10) * Read/write 'SCOM - HV Indirect Data Register' to get/set the value. */ - +static void pnv_phb4_xscom_write(QTestState *qts, uint32_t reg, uint64_t val) +{ + qtest_writeq(qts, pnv_phb4_xscom_addr(PHB_SCOM_HV_IND_ADDR), + PPC_BIT(0) | reg); + qtest_writeq(qts, pnv_phb4_xscom_addr(PHB_SCOM_HV_IND_DATA), val); +} static uint64_t pnv_phb4_xscom_read(QTestState *qts, uint32_t reg) { qtest_writeq(qts, pnv_phb4_xscom_addr(PHB_SCOM_HV_IND_ADDR), @@ -61,6 +66,26 @@ static void phb4_reset_test(QTestState *qts) ==, 0xC009000000000000); } +/* Check sticky-reset */ +static void phb4_sticky_rst_test(QTestState *qts) +{ + uint64_t val; + + /* + * Sticky reset test of PHB_PBL_ERR_STATUS. + * + * Write all 1's to reg PHB_PBL_ERR_INJECT. + * Updated value will be copied to reg PHB_PBL_ERR_STATUS. + * + * Reset PBL core by setting PHB_PCIE_CRESET_PBL in reg PHB_PCIE_CRESET. + * Verify the sticky bits are still set. + */ + pnv_phb4_xscom_write(qts, PHB_PBL_ERR_INJECT, PPC_BITMASK(0, 63)); + pnv_phb4_xscom_write(qts, PHB_PCIE_CRESET, PHB_PCIE_CRESET_PBL); /*Reset*/ + val = pnv_phb4_xscom_read(qts, PHB_PBL_ERR_STATUS); + g_assert_cmpuint(val, ==, (PPC_BITMASK(0, 9) | PPC_BITMASK(12, 63))); +} + static void test_phb4(void) { QTestState *qts = NULL; @@ -73,6 +98,9 @@ static void test_phb4(void) /* Check reset value of a register */ phb4_reset_test(qts); + /* Check sticky reset of a register */ + phb4_sticky_rst_test(qts); + qtest_quit(qts); } From patchwork Thu Mar 21 10:04:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Saif Abrar X-Patchwork-Id: 1914346 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=ZK3HiHm/; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4V0h2B60vgz1yWy for ; Thu, 21 Mar 2024 21:06:42 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnFIM-00074T-J1; Thu, 21 Mar 2024 06:05:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFI5-0006z7-CY; Thu, 21 Mar 2024 06:04:53 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFI2-0007ZI-Rj; Thu, 21 Mar 2024 06:04:53 -0400 Received: from pps.filterd (m0353728.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 42L9tqYE032400; Thu, 21 Mar 2024 10:04:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=oC+gnTxg7vjj+JAMmKjhF1ZfKiz5vQKgNmSpxequyW0=; b=ZK3HiHm/W3xscNsjdEhikDMqYugpd2+7x32l2F8BGZ7//54WOQRxX/W2cGR3R6srBHDu I8DY293JM4mR0nSFCr+/4AxzzoOdQsA3/mwdEAwwIfUHgz8NPFBkmpfY8Mycq1hpLrsN ZYjG5nv0EwFGSeytk2RBV0iauxkhEkax63W8X0Yo18LUomJRc8EZ15MYux4UbCsOYaBK pwEuMubgx/ASL6PXJtDEYZZsQuIykUCuy8siDY5EI0z3wVBscFxjdbA6y7jIodDoJ975 z1jZn1p1NxQI0MjYZFC348+g1oXoqqn2vWC8Lkha/CWQ4pbxfsbaO81JbGDTLuycGQU0 aQ== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0gta09d8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:40 +0000 Received: from m0353728.ppops.net (m0353728.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 42LA4dHt019725; Thu, 21 Mar 2024 10:04:39 GMT Received: from ppma12.dal12v.mail.ibm.com (dc.9e.1632.ip4.static.sl-reverse.com [50.22.158.220]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0gta09d7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:39 +0000 Received: from pps.filterd (ppma12.dal12v.mail.ibm.com [127.0.0.1]) by ppma12.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 42L8N3hM017266; Thu, 21 Mar 2024 10:04:38 GMT Received: from smtprelay02.dal12v.mail.ibm.com ([172.16.1.4]) by ppma12.dal12v.mail.ibm.com (PPS) with ESMTPS id 3wwnrtmh7m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:38 +0000 Received: from smtpav04.dal12v.mail.ibm.com (smtpav04.dal12v.mail.ibm.com [10.241.53.103]) by smtprelay02.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 42LA4Z0E44630316 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 21 Mar 2024 10:04:38 GMT Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C12A658056; Thu, 21 Mar 2024 10:04:35 +0000 (GMT) Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2EC9258065; Thu, 21 Mar 2024 10:04:35 +0000 (GMT) Received: from gfwr516.rchland.ibm.com (unknown [9.10.239.105]) by smtpav04.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 21 Mar 2024 10:04:35 +0000 (GMT) From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH 04/10] pnv/phb4: Implement read-only and write-only bits of registers Date: Thu, 21 Mar 2024 05:04:16 -0500 Message-Id: <20240321100422.5347-5-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> References: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: tAlCiII9x4wgr8pLXPyYvOFxHtLr_q9q X-Proofpoint-GUID: uRUglKNcNg7Aes-FcJ9QqFprFA2lH9zY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-21_06,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 phishscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 suspectscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2403140000 definitions=main-2403210069 Received-SPF: none client-ip=148.163.156.1; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org SW cannot write the read-only(RO) bits of a register and write-only(WO) bits of a register return 0 when read. Added ro_mask[] for each register that defines which bits in that register are RO. When writing to a register, the RO-bits are not updated. When reading a register, clear the WO bits and return the updated value. Tested the registers PHB_DMA_SYNC, PHB_PCIE_HOTPLUG_STATUS, PHB_PCIE_LMR, PHB_PCIE_DLP_TRWCTL, PHB_LEM_ERROR_AND_MASK and PHB_LEM_ERROR_OR_MASK by writing all 1's and reading back the value. The WO bits in these registers should read back as 0. Signed-off-by: Saif Abrar --- hw/pci-host/pnv_phb4.c | 77 ++++++++++++++++++++++++++--- include/hw/pci-host/pnv_phb4.h | 7 +++ include/hw/pci-host/pnv_phb4_regs.h | 19 +++++-- tests/qtest/pnv-phb4-test.c | 60 +++++++++++++++++++++- 4 files changed, 150 insertions(+), 13 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index b3a83837f8..a81763f34c 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -735,6 +735,10 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, return; } + /* Update 'val' according to the register's RO-mask */ + val = (phb->regs[off >> 3] & phb->ro_mask[off >> 3]) | + (val & ~(phb->ro_mask[off >> 3])); + /* Record whether it changed */ changed = phb->regs[off >> 3] != val; @@ -808,7 +812,7 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, case PHB_TCE_TAG_ENABLE: case PHB_INT_NOTIFY_ADDR: case PHB_INT_NOTIFY_INDEX: - case PHB_DMARD_SYNC: + case PHB_DMA_SYNC: break; /* Noise on anything else */ @@ -846,7 +850,7 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) case PHB_VERSION: return PNV_PHB4_PEC_GET_CLASS(phb->pec)->version; - /* Read-only */ + /* Read-only */ case PHB_PHB4_GEN_CAP: return 0xe4b8000000000000ull; case PHB_PHB4_TCE_CAP: @@ -856,18 +860,49 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) case PHB_PHB4_EEH_CAP: return phb->big_phb ? 0x2000000000000000ull : 0x1000000000000000ull; + /* Write-only, read will return zeros */ + case PHB_LEM_ERROR_AND_MASK: + case PHB_LEM_ERROR_OR_MASK: + return 0; + case PHB_PCIE_DLP_TRWCTL: + val &= ~PHB_PCIE_DLP_TRWCTL_WREN; + return val; /* IODA table accesses */ case PHB_IODA_DATA0: return pnv_phb4_ioda_read(phb); + /* + * DMA sync: make it look like it's complete, + * clear write-only read/write start sync bits. + */ + case PHB_DMA_SYNC: + val = PHB_DMA_SYNC_RD_COMPLETE | + ~(PHB_DMA_SYNC_RD_START | PHB_DMA_SYNC_WR_START); + return val; + + /* + * PCI-E Stack registers + */ + case PHB_PCIE_SCR: + val |= PHB_PCIE_SCR_PLW_X16; /* RO bit */ + break; + /* Link training always appears trained */ case PHB_PCIE_DLP_TRAIN_CTL: /* TODO: Do something sensible with speed ? */ - return PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT; + val |= PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT; + return val; + + case PHB_PCIE_HOTPLUG_STATUS: + /* Clear write-only bit */ + val &= ~PHB_PCIE_HPSTAT_RESAMPLE; + return val; - /* DMA read sync: make it look like it's complete */ - case PHB_DMARD_SYNC: - return PHB_DMARD_SYNC_COMPLETE; + /* Link Management Register */ + case PHB_PCIE_LMR: + /* These write-only bits always read as 0 */ + val &= ~(PHB_PCIE_LMR_CHANGELW | PHB_PCIE_LMR_RETRAINLINK); + return val; /* Silent simple reads */ case PHB_LSI_SOURCE_ID: @@ -1712,6 +1747,33 @@ static PCIIOMMUOps pnv_phb4_iommu_ops = { .get_address_space = pnv_phb4_dma_iommu, }; +static void pnv_phb4_ro_mask_init(PnvPHB4 *phb) +{ + /* Clear RO-mask to make all regs as R/W by default */ + memset(phb->ro_mask, 0x0, PNV_PHB4_NUM_REGS * sizeof(uint64_t)); + + /* + * Set register specific RO-masks + */ + + /* PBL - Error Injection Register (0x1910) */ + phb->ro_mask[PHB_PBL_ERR_INJECT >> 3] = + PPC_BITMASK(0, 23) | PPC_BITMASK(28, 35) | PPC_BIT(38) | PPC_BIT(46) | + PPC_BITMASK(49, 51) | PPC_BITMASK(55, 63); + + /* Reserved bits[60:63] */ + phb->ro_mask[PHB_TXE_ERR_LEM_ENABLE >> 3] = + phb->ro_mask[PHB_TXE_ERR_AIB_FENCE_ENABLE >> 3] = PPC_BITMASK(60, 63); + /* Reserved bits[36:63] */ + phb->ro_mask[PHB_RXE_TCE_ERR_LEM_ENABLE >> 3] = + phb->ro_mask[PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE >> 3] = PPC_BITMASK(36, 63); + /* Reserved bits[40:63] */ + phb->ro_mask[PHB_ERR_LEM_ENABLE >> 3] = + phb->ro_mask[PHB_ERR_AIB_FENCE_ENABLE >> 3] = PPC_BITMASK(40, 63); + + /* TODO: Add more RO-masks as regs are implemented in the model */ +} + static void pnv_phb4_err_reg_reset(PnvPHB4 *phb) { STICKY_RST(PHB_ERR_STATUS, 0, PPC_BITMASK(0, 33)); @@ -1782,6 +1844,9 @@ static void pnv_phb4_instance_init(Object *obj) /* XIVE interrupt source object */ object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE); + + /* Initialize RO-mask of registers */ + pnv_phb4_ro_mask_init(phb); } void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb) diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 3212e68160..91e81eee0e 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -94,6 +94,13 @@ struct PnvPHB4 { uint64_t regs[PNV_PHB4_NUM_REGS]; MemoryRegion mr_regs; + /* + * Read-only bitmask for registers + * Bit value: 1 => RO bit + * 0 => RW bit + */ + uint64_t ro_mask[PNV_PHB4_NUM_REGS]; + /* Extra SCOM-only register */ uint64_t scom_hv_ind_addr_reg; diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_phb4_regs.h index df5e86d29a..391d6a89ea 100644 --- a/include/hw/pci-host/pnv_phb4_regs.h +++ b/include/hw/pci-host/pnv_phb4_regs.h @@ -180,9 +180,11 @@ #define PHB_M64_AOMASK 0x1d0 #define PHB_M64_UPPER_BITS 0x1f0 #define PHB_NXLATE_PREFIX 0x1f8 -#define PHB_DMARD_SYNC 0x200 -#define PHB_DMARD_SYNC_START PPC_BIT(0) -#define PHB_DMARD_SYNC_COMPLETE PPC_BIT(1) +#define PHB_DMA_SYNC 0x200 +#define PHB_DMA_SYNC_RD_START PPC_BIT(0) +#define PHB_DMA_SYNC_RD_COMPLETE PPC_BIT(1) +#define PHB_DMA_SYNC_WR_START PPC_BIT(2) +#define PHB_DMA_SYNC_WR_COMPLETE PPC_BIT(3) #define PHB_RTC_INVALIDATE 0x208 #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0) #define PHB_RTC_INVALIDATE_RID PPC_BITMASK(16, 31) @@ -395,8 +397,8 @@ #define PHB_PCIE_SCR 0x1A00 #define PHB_PCIE_SCR_SLOT_CAP PPC_BIT(15) #define PHB_PCIE_SCR_MAXLINKSPEED PPC_BITMASK(32, 35) +#define PHB_PCIE_SCR_PLW_X16 PPC_BIT(41) /* x16 */ #define PHB_PCIE_BNR 0x1A08 - #define PHB_PCIE_CRESET 0x1A10 #define PHB_PCIE_CRESET_CFG_CORE PPC_BIT(0) #define PHB_PCIE_CRESET_TLDLP PPC_BIT(1) @@ -405,7 +407,14 @@ #define PHB_PCIE_CRESET_PIPE_N PPC_BIT(4) #define PHB_PCIE_CRESET_REFCLK_N PPC_BIT(8) #define PHB_PCIE_HOTPLUG_STATUS 0x1A20 +#define PHB_PCIE_HPSTAT_SIMDIAG PPC_BIT(3) +#define PHB_PCIE_HPSTAT_RESAMPLE PPC_BIT(9) #define PHB_PCIE_HPSTAT_PRESENCE PPC_BIT(10) +#define PHB_PCIE_HPSTAT_LINKACTIVE PPC_BIT(12) +#define PHB_PCIE_LMR 0x1A30 +#define PHB_PCIE_LMR_CHANGELW PPC_BIT(0) +#define PHB_PCIE_LMR_RETRAINLINK PPC_BIT(1) +#define PHB_PCIE_LMR_LINKACTIVE PPC_BIT(8) #define PHB_PCIE_DLP_TRAIN_CTL 0x1A40 #define PHB_PCIE_DLP_LINK_WIDTH PPC_BITMASK(30, 35) @@ -433,7 +442,7 @@ #define PHB_PCIE_DLP_TRWCTL 0x1A80 #define PHB_PCIE_DLP_TRWCTL_EN PPC_BIT(0) - +#define PHB_PCIE_DLP_TRWCTL_WREN PPC_BIT(1) #define PHB_PCIE_DLP_ERRLOG1 0x1AA0 #define PHB_PCIE_DLP_ERRLOG2 0x1AA8 #define PHB_PCIE_DLP_ERR_STATUS 0x1AB0 diff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c index 708df3867c..0c8e58dd5f 100644 --- a/tests/qtest/pnv-phb4-test.c +++ b/tests/qtest/pnv-phb4-test.c @@ -75,7 +75,8 @@ static void phb4_sticky_rst_test(QTestState *qts) * Sticky reset test of PHB_PBL_ERR_STATUS. * * Write all 1's to reg PHB_PBL_ERR_INJECT. - * Updated value will be copied to reg PHB_PBL_ERR_STATUS. + * RO-only bits will not be written and + * updated value will be copied to reg PHB_PBL_ERR_STATUS. * * Reset PBL core by setting PHB_PCIE_CRESET_PBL in reg PHB_PCIE_CRESET. * Verify the sticky bits are still set. @@ -83,7 +84,59 @@ static void phb4_sticky_rst_test(QTestState *qts) pnv_phb4_xscom_write(qts, PHB_PBL_ERR_INJECT, PPC_BITMASK(0, 63)); pnv_phb4_xscom_write(qts, PHB_PCIE_CRESET, PHB_PCIE_CRESET_PBL); /*Reset*/ val = pnv_phb4_xscom_read(qts, PHB_PBL_ERR_STATUS); - g_assert_cmpuint(val, ==, (PPC_BITMASK(0, 9) | PPC_BITMASK(12, 63))); + g_assert_cmpuint(val, ==, 0xF00DFD8E00); +} + +/* Check that write-only bits/regs return 0 when read */ +static void phb4_writeonly_read_test(QTestState *qts) +{ + uint64_t val; + + /* + * Set all bits of PHB_DMA_SYNC, + * bits 0 and 2 are write-only and should be read as 0. + */ + pnv_phb4_xscom_write(qts, PHB_DMA_SYNC, PPC_BITMASK(0, 63)); + val = pnv_phb4_xscom_read(qts, PHB_DMA_SYNC); + g_assert_cmpuint(val & PPC_BIT(0), ==, 0x0); + g_assert_cmpuint(val & PPC_BIT(2), ==, 0x0); + + /* + * Set all bits of PHB_PCIE_HOTPLUG_STATUS, + * bit 9 is write-only and should be read as 0. + */ + pnv_phb4_xscom_write(qts, PHB_PCIE_HOTPLUG_STATUS, PPC_BITMASK(0, 63)); + val = pnv_phb4_xscom_read(qts, PHB_PCIE_HOTPLUG_STATUS); + g_assert_cmpuint(val & PPC_BIT(9), ==, 0x0); + + /* + * Set all bits of PHB_PCIE_LMR, + * bits 0 and 1 are write-only and should be read as 0. + */ + pnv_phb4_xscom_write(qts, PHB_PCIE_LMR, PPC_BITMASK(0, 63)); + val = pnv_phb4_xscom_read(qts, PHB_PCIE_LMR); + g_assert_cmpuint(val & PPC_BIT(0), ==, 0x0); + g_assert_cmpuint(val & PPC_BIT(1), ==, 0x0); + + /* + * Set all bits of PHB_PCIE_DLP_TRWCTL, + * write-only bit-1 should be read as 0. + */ + pnv_phb4_xscom_write(qts, PHB_PCIE_DLP_TRWCTL, PPC_BITMASK(0, 63)); + val = pnv_phb4_xscom_read(qts, PHB_PCIE_DLP_TRWCTL); + g_assert_cmpuint(val & PPC_BIT(1), ==, 0x0); + + /* + * Set all bits of PHB_LEM_ERROR_AND_MASK, PHB_LEM_ERROR_OR_MASK, + * both regs are write-only and should be read as 0. + */ + pnv_phb4_xscom_write(qts, PHB_LEM_ERROR_AND_MASK, PPC_BITMASK(0, 63)); + val = pnv_phb4_xscom_read(qts, PHB_LEM_ERROR_AND_MASK); + g_assert_cmpuint(val, ==, 0x0); + + pnv_phb4_xscom_write(qts, PHB_LEM_ERROR_OR_MASK, PPC_BITMASK(0, 63)); + val = pnv_phb4_xscom_read(qts, PHB_LEM_ERROR_OR_MASK); + g_assert_cmpuint(val, ==, 0x0); } static void test_phb4(void) @@ -101,6 +154,9 @@ static void test_phb4(void) /* Check sticky reset of a register */ phb4_sticky_rst_test(qts); + /* Check write-only logic */ + phb4_writeonly_read_test(qts); + qtest_quit(qts); } From patchwork Thu Mar 21 10:04:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Saif Abrar X-Patchwork-Id: 1914356 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=irZgMp9k; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4V0h332pf1z1yWy for ; Thu, 21 Mar 2024 21:07:27 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnFIO-00075T-90; Thu, 21 Mar 2024 06:05:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFIA-00070S-Ul; Thu, 21 Mar 2024 06:04:59 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFI8-0007Yc-Bk; Thu, 21 Mar 2024 06:04:58 -0400 Received: from pps.filterd (m0356517.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 42L6UNuY019879; Thu, 21 Mar 2024 10:04:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=/K1k+8D//kLONqr0zeT0bXxJ4z/so6cOeQjMH5vDEwM=; b=irZgMp9knLgxKiIScPMylqaBi+dIziuXKqgFlTD/MbmgDfIHwWyGpSaAjWGLZbXiPylJ kNG2zBTamI+10syCYtmcBQr1atqGngJum4wvfpE8koOG1sbKqd++ro3AIn5NOX8NbgD8 fRC3LtNdG1chSvpCbTUmgmQI4qPNbcb8wFdGmJC9pIh7xxwygzy377+Qr2xpTEl/VfuZ D6Cncj9IED2QHXL+Gacgwi+P91V/ycw9ysqBwr3IYJNVJ6C78nlIwmcoY7klABh3DdLh YmADKKiVikLEra3EMa+GBelndjrtbyhoZdAVfvglqQl9pZvYjElvMWAzHr9ONVjlLLa5 +Q== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0e5ugmbd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:41 +0000 Received: from m0356517.ppops.net (m0356517.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 42LA4fVm022485; Thu, 21 Mar 2024 10:04:41 GMT Received: from ppma12.dal12v.mail.ibm.com (dc.9e.1632.ip4.static.sl-reverse.com [50.22.158.220]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0e5ugmbb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:41 +0000 Received: from pps.filterd (ppma12.dal12v.mail.ibm.com [127.0.0.1]) by ppma12.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 42L91AIo017231; Thu, 21 Mar 2024 10:04:40 GMT Received: from smtprelay03.wdc07v.mail.ibm.com ([172.16.1.70]) by ppma12.dal12v.mail.ibm.com (PPS) with ESMTPS id 3wwnrtmh7s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:40 +0000 Received: from smtpav04.dal12v.mail.ibm.com (smtpav04.dal12v.mail.ibm.com [10.241.53.103]) by smtprelay03.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 42LA4aCU26608286 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 21 Mar 2024 10:04:38 GMT Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4FDED58062; Thu, 21 Mar 2024 10:04:36 +0000 (GMT) Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CF1E958069; Thu, 21 Mar 2024 10:04:35 +0000 (GMT) Received: from gfwr516.rchland.ibm.com (unknown [9.10.239.105]) by smtpav04.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 21 Mar 2024 10:04:35 +0000 (GMT) From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH 05/10] pnv/phb4: Implement write-clear and return 1's on unimplemented reg read Date: Thu, 21 Mar 2024 05:04:17 -0500 Message-Id: <20240321100422.5347-6-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> References: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: IIdQtSgiBef9Bcoj182CCgjzN7tEZ_5y X-Proofpoint-GUID: N_O6ZsDbL3O8EV-wSfVHBY-latdfV51Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-21_06,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2403140000 definitions=main-2403210069 Received-SPF: none client-ip=148.163.156.1; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Implement write-1-to-clear and write-X-to-clear logic. Update registers with silent simple read and write. Return all 1's when an unimplemented/reserved register is read. Test that reading address 0x0 returns all 1's (i.e. -1). Signed-off-by: Saif Abrar Reviewed-by: Cédric Le Goater --- hw/pci-host/pnv_phb4.c | 190 ++++++++++++++++++++++------ include/hw/pci-host/pnv_phb4_regs.h | 12 +- tests/qtest/pnv-phb4-test.c | 9 ++ 3 files changed, 170 insertions(+), 41 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index a81763f34c..4e3a6b37f9 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -683,8 +683,41 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, return; } - /* Handle masking */ + /* Handle RO, W1C, WxC and masking */ switch (off) { + /* W1C: Write-1-to-Clear registers */ + case PHB_TXE_ERR_STATUS: + case PHB_RXE_ARB_ERR_STATUS: + case PHB_RXE_MRG_ERR_STATUS: + case PHB_RXE_TCE_ERR_STATUS: + case PHB_ERR_STATUS: + case PHB_REGB_ERR_STATUS: + case PHB_PCIE_DLP_ERRLOG1: + case PHB_PCIE_DLP_ERRLOG2: + case PHB_PCIE_DLP_ERR_STATUS: + case PHB_PBL_ERR_STATUS: + phb->regs[off >> 3] &= ~val; + return; + + /* WxC: Clear register on any write */ + case PHB_PBL_ERR1_STATUS: + case PHB_PBL_ERR_LOG_0 ... PHB_PBL_ERR_LOG_1: + case PHB_REGB_ERR1_STATUS: + case PHB_REGB_ERR_LOG_0 ... PHB_REGB_ERR_LOG_1: + case PHB_TXE_ERR1_STATUS: + case PHB_TXE_ERR_LOG_0 ... PHB_TXE_ERR_LOG_1: + case PHB_RXE_ARB_ERR1_STATUS: + case PHB_RXE_ARB_ERR_LOG_0 ... PHB_RXE_ARB_ERR_LOG_1: + case PHB_RXE_MRG_ERR1_STATUS: + case PHB_RXE_MRG_ERR_LOG_0 ... PHB_RXE_MRG_ERR_LOG_1: + case PHB_RXE_TCE_ERR1_STATUS: + case PHB_RXE_TCE_ERR_LOG_0 ... PHB_RXE_TCE_ERR_LOG_1: + case PHB_ERR1_STATUS: + case PHB_ERR_LOG_0 ... PHB_ERR_LOG_1: + phb->regs[off >> 3] = 0; + return; + + /* Write value updated by masks */ case PHB_LSI_SOURCE_ID: val &= PHB_LSI_SRC_ID; break; @@ -723,7 +756,6 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, case PHB_LEM_WOF: val = 0; break; - /* TODO: More regs ..., maybe create a table with masks... */ /* Read only registers */ case PHB_CPU_LOADSTORE_STATUS: @@ -732,6 +764,12 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, case PHB_PHB4_TCE_CAP: case PHB_PHB4_IRQ_CAP: case PHB_PHB4_EEH_CAP: + case PHB_VERSION: + case PHB_DMA_CHAN_STATUS: + case PHB_TCE_TAG_STATUS: + case PHB_PBL_BUF_STATUS: + case PHB_PCIE_BNR: + case PHB_PCIE_PHY_RXEQ_STAT_G3_00_03 ... PHB_PCIE_PHY_RXEQ_STAT_G5_12_15: return; } @@ -752,6 +790,7 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, pnv_phb4_update_all_msi_regions(phb); } break; + case PHB_M32_START_ADDR: case PHB_M64_UPPER_BITS: if (changed) { @@ -797,27 +836,63 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, break; /* Silent simple writes */ - case PHB_ASN_CMPM: - case PHB_CONFIG_ADDRESS: - case PHB_IODA_ADDR: - case PHB_TCE_KILL: - case PHB_TCE_SPEC_CTL: - case PHB_PEST_BAR: - case PHB_PELTV_BAR: + /* PHB Fundamental register set A */ + case PHB_CONFIG_DATA ... PHB_LOCK1: case PHB_RTT_BAR: - case PHB_LEM_FIR_ACCUM: - case PHB_LEM_ERROR_MASK: - case PHB_LEM_ACTION0: - case PHB_LEM_ACTION1: - case PHB_TCE_TAG_ENABLE: + case PHB_PELTV_BAR: + case PHB_PEST_BAR: + case PHB_CAPI_CMPM ... PHB_M64_AOMASK: + case PHB_NXLATE_PREFIX ... PHB_DMA_SYNC: + case PHB_TCE_KILL ... PHB_IODA_ADDR: + case PHB_PAPR_ERR_INJ_CTL ... PHB_PAPR_ERR_INJ_MASK: case PHB_INT_NOTIFY_ADDR: case PHB_INT_NOTIFY_INDEX: - case PHB_DMA_SYNC: - break; + /* Fundamental register set B */ + case PHB_AIB_FENCE_CTRL ... PHB_Q_DMA_R: + /* FIR & Error registers */ + case PHB_LEM_FIR_ACCUM: + case PHB_LEM_ERROR_MASK: + case PHB_LEM_ACTION0 ... PHB_LEM_WOF: + case PHB_ERR_INJECT ... PHB_ERR_AIB_FENCE_ENABLE: + case PHB_ERR_STATUS_MASK ... PHB_ERR1_STATUS_MASK: + case PHB_TXE_ERR_INJECT ... PHB_TXE_ERR_AIB_FENCE_ENABLE: + case PHB_TXE_ERR_STATUS_MASK ... PHB_TXE_ERR1_STATUS_MASK: + case PHB_RXE_ARB_ERR_INJECT ... PHB_RXE_ARB_ERR_AIB_FENCE_ENABLE: + case PHB_RXE_ARB_ERR_STATUS_MASK ... PHB_RXE_ARB_ERR1_STATUS_MASK: + case PHB_RXE_MRG_ERR_INJECT ... PHB_RXE_MRG_ERR_AIB_FENCE_ENABLE: + case PHB_RXE_MRG_ERR_STATUS_MASK ... PHB_RXE_MRG_ERR1_STATUS_MASK: + case PHB_RXE_TCE_ERR_INJECT ... PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE: + case PHB_RXE_TCE_ERR_STATUS_MASK ... PHB_RXE_TCE_ERR1_STATUS_MASK: + /* Performance monitor & Debug registers */ + case PHB_TRACE_CONTROL ... PHB_PERFMON_CTR1: + /* REGB Registers */ + /* PBL core */ + case PHB_PBL_CONTROL: + case PHB_PBL_TIMEOUT_CTRL: + case PHB_PBL_NPTAG_ENABLE: + case PHB_PBL_SYS_LINK_INIT: + case PHB_PBL_ERR_INF_ENABLE ... PHB_PBL_ERR_FAT_ENABLE: + case PHB_PBL_ERR_STATUS_MASK ... PHB_PBL_ERR1_STATUS_MASK: + /* PCI-E stack */ + case PHB_PCIE_SCR: + case PHB_PCIE_DLP_STR ... PHB_PCIE_HOTPLUG_STATUS: + case PHB_PCIE_LMR ... PHB_PCIE_DLP_LSR: + case PHB_PCIE_DLP_RXMGN: + case PHB_PCIE_DLP_LANEZEROCTL ... PHB_PCIE_DLP_TRCRDDATA: + case PHB_PCIE_DLP_ERR_COUNTERS: + case PHB_PCIE_DLP_EIC ... PHB_PCIE_LANE_EQ_CNTL23: + case PHB_PCIE_TRACE_CTRL: + case PHB_PCIE_MISC_STRAP ... PHB_PCIE_PHY_EQ_CTL: + /* Error registers */ + case PHB_REGB_ERR_INJECT: + case PHB_REGB_ERR_INF_ENABLE ... PHB_REGB_ERR_FAT_ENABLE: + case PHB_REGB_ERR_STATUS_MASK ... PHB_REGB_ERR1_STATUS_MASK: + break; /* Noise on anything else */ default: - qemu_log_mask(LOG_UNIMP, "phb4: reg_write 0x%"PRIx64"=%"PRIx64"\n", + qemu_log_mask(LOG_UNIMP, + "phb4: unimplemented reg_write 0x%"PRIx64"=%"PRIx64"\n", off, val); } } @@ -905,36 +980,75 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) return val; /* Silent simple reads */ + /* PHB Fundamental register set A */ case PHB_LSI_SOURCE_ID: + case PHB_DMA_CHAN_STATUS: case PHB_CPU_LOADSTORE_STATUS: - case PHB_ASN_CMPM: + case PHB_CONFIG_DATA ... PHB_LOCK1: case PHB_PHB4_CONFIG: + case PHB_RTT_BAR: + case PHB_PELTV_BAR: case PHB_M32_START_ADDR: - case PHB_CONFIG_ADDRESS: - case PHB_IODA_ADDR: - case PHB_RTC_INVALIDATE: - case PHB_TCE_KILL: - case PHB_TCE_SPEC_CTL: case PHB_PEST_BAR: - case PHB_PELTV_BAR: - case PHB_RTT_BAR: + case PHB_CAPI_CMPM: + case PHB_M64_AOMASK: case PHB_M64_UPPER_BITS: - case PHB_CTRLR: - case PHB_LEM_FIR_ACCUM: - case PHB_LEM_ERROR_MASK: - case PHB_LEM_ACTION0: - case PHB_LEM_ACTION1: - case PHB_TCE_TAG_ENABLE: + case PHB_NXLATE_PREFIX: + case PHB_RTC_INVALIDATE ... PHB_IODA_ADDR: + case PHB_PAPR_ERR_INJ_CTL ... PHB_ETU_ERR_SUMMARY: case PHB_INT_NOTIFY_ADDR: case PHB_INT_NOTIFY_INDEX: - case PHB_Q_DMA_R: - case PHB_ETU_ERR_SUMMARY: - break; - - /* Noise on anything else */ + /* Fundamental register set B */ + case PHB_CTRLR: + case PHB_AIB_FENCE_CTRL ... PHB_Q_DMA_R: + case PHB_TCE_TAG_STATUS: + /* FIR & Error registers */ + case PHB_LEM_FIR_ACCUM ... PHB_LEM_ERROR_MASK: + case PHB_LEM_ACTION0 ... PHB_LEM_WOF: + case PHB_ERR_STATUS ... PHB_ERR_AIB_FENCE_ENABLE: + case PHB_ERR_LOG_0 ... PHB_ERR1_STATUS_MASK: + case PHB_TXE_ERR_STATUS ... PHB_TXE_ERR_AIB_FENCE_ENABLE: + case PHB_TXE_ERR_LOG_0 ... PHB_TXE_ERR1_STATUS_MASK: + case PHB_RXE_ARB_ERR_STATUS ... PHB_RXE_ARB_ERR_AIB_FENCE_ENABLE: + case PHB_RXE_ARB_ERR_LOG_0 ... PHB_RXE_ARB_ERR1_STATUS_MASK: + case PHB_RXE_MRG_ERR_STATUS ... PHB_RXE_MRG_ERR_AIB_FENCE_ENABLE: + case PHB_RXE_MRG_ERR_LOG_0 ... PHB_RXE_MRG_ERR1_STATUS_MASK: + case PHB_RXE_TCE_ERR_STATUS ... PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE: + case PHB_RXE_TCE_ERR_LOG_0 ... PHB_RXE_TCE_ERR1_STATUS_MASK: + /* Performance monitor & Debug registers */ + case PHB_TRACE_CONTROL ... PHB_PERFMON_CTR1: + /* REGB Registers */ + /* PBL core */ + case PHB_PBL_CONTROL: + case PHB_PBL_TIMEOUT_CTRL: + case PHB_PBL_NPTAG_ENABLE: + case PHB_PBL_SYS_LINK_INIT: + case PHB_PBL_BUF_STATUS: + case PHB_PBL_ERR_STATUS ... PHB_PBL_ERR_INJECT: + case PHB_PBL_ERR_INF_ENABLE ... PHB_PBL_ERR_FAT_ENABLE: + case PHB_PBL_ERR_LOG_0 ... PHB_PBL_ERR1_STATUS_MASK: + /* PCI-E stack */ + case PHB_PCIE_BNR ... PHB_PCIE_DLP_STR: + case PHB_PCIE_DLP_LANE_PWR: + case PHB_PCIE_DLP_LSR: + case PHB_PCIE_DLP_RXMGN: + case PHB_PCIE_DLP_LANEZEROCTL ... PHB_PCIE_DLP_CTL: + case PHB_PCIE_DLP_TRCRDDATA: + case PHB_PCIE_DLP_ERRLOG1 ... PHB_PCIE_DLP_ERR_COUNTERS: + case PHB_PCIE_DLP_EIC ... PHB_PCIE_LANE_EQ_CNTL23: + case PHB_PCIE_TRACE_CTRL: + case PHB_PCIE_MISC_STRAP ... PHB_PCIE_PHY_RXEQ_STAT_G5_12_15: + /* Error registers */ + case PHB_REGB_ERR_STATUS ... PHB_REGB_ERR_INJECT: + case PHB_REGB_ERR_INF_ENABLE ... PHB_REGB_ERR_FAT_ENABLE: + case PHB_REGB_ERR_LOG_0 ... PHB_REGB_ERR1_STATUS_MASK: + break; + + /* Noise on unimplemented read, return all 1's */ default: - qemu_log_mask(LOG_UNIMP, "phb4: reg_read 0x%"PRIx64"=%"PRIx64"\n", - off, val); + qemu_log_mask(LOG_UNIMP, "phb4: unimplemented reg_read 0x%"PRIx64"\n", + off); + val = ~0ull; } return val; } diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_phb4_regs.h index 391d6a89ea..c1d5a83271 100644 --- a/include/hw/pci-host/pnv_phb4_regs.h +++ b/include/hw/pci-host/pnv_phb4_regs.h @@ -372,6 +372,7 @@ #define P32_CAP 0x228 #define P32_CTL 0x22C #define P32_STAT 0x230 + /* PHB4 REGB registers */ /* PBL core */ @@ -406,6 +407,7 @@ #define PHB_PCIE_CRESET_PERST_N PPC_BIT(3) #define PHB_PCIE_CRESET_PIPE_N PPC_BIT(4) #define PHB_PCIE_CRESET_REFCLK_N PPC_BIT(8) +#define PHB_PCIE_DLP_STR 0x1A18 #define PHB_PCIE_HOTPLUG_STATUS 0x1A20 #define PHB_PCIE_HPSTAT_SIMDIAG PPC_BIT(3) #define PHB_PCIE_HPSTAT_RESAMPLE PPC_BIT(9) @@ -416,6 +418,7 @@ #define PHB_PCIE_LMR_RETRAINLINK PPC_BIT(1) #define PHB_PCIE_LMR_LINKACTIVE PPC_BIT(8) +#define PHB_PCIE_DLP_LANE_PWR 0x1A38 #define PHB_PCIE_DLP_TRAIN_CTL 0x1A40 #define PHB_PCIE_DLP_LINK_WIDTH PPC_BITMASK(30, 35) #define PHB_PCIE_DLP_LINK_SPEED PPC_BITMASK(36, 39) @@ -435,18 +438,21 @@ #define PHB_PCIE_DLP_DL_PGRESET PPC_BIT(22) #define PHB_PCIE_DLP_TRAINING PPC_BIT(20) #define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19) - +#define PHB_PCIE_DLP_LSR 0x1A48 +#define PHB_PCIE_DLP_RXMGN 0x1A50 +#define PHB_PCIE_DLP_LANEZEROCTL 0x1A70 #define PHB_PCIE_DLP_CTL 0x1A78 #define PHB_PCIE_DLP_CTL_BYPASS_PH2 PPC_BIT(4) #define PHB_PCIE_DLP_CTL_BYPASS_PH3 PPC_BIT(5) - #define PHB_PCIE_DLP_TRWCTL 0x1A80 #define PHB_PCIE_DLP_TRWCTL_EN PPC_BIT(0) #define PHB_PCIE_DLP_TRWCTL_WREN PPC_BIT(1) +#define PHB_PCIE_DLP_TRCRDDATA 0x1A88 #define PHB_PCIE_DLP_ERRLOG1 0x1AA0 #define PHB_PCIE_DLP_ERRLOG2 0x1AA8 #define PHB_PCIE_DLP_ERR_STATUS 0x1AB0 #define PHB_PCIE_DLP_ERR_COUNTERS 0x1AB8 +#define PHB_PCIE_DLP_EIC 0x1AC8 #define PHB_PCIE_LANE_EQ_CNTL0 0x1AD0 #define PHB_PCIE_LANE_EQ_CNTL1 0x1AD8 @@ -458,6 +464,7 @@ #define PHB_PCIE_LANE_EQ_CNTL23 0x1B08 /* DD1 only */ #define PHB_PCIE_TRACE_CTRL 0x1B20 #define PHB_PCIE_MISC_STRAP 0x1B30 +#define PHB_PCIE_PHY_EQ_CTL 0x1B38 #define PHB_PCIE_PHY_RXEQ_STAT_G3_00_03 0x1B40 #define PHB_PCIE_PHY_RXEQ_STAT_G5_12_15 0x1B98 @@ -591,5 +598,4 @@ #define IODA3_PEST1_FAIL_ADDR PPC_BITMASK(3, 63) - #endif /* PCI_HOST_PNV_PHB4_REGS_H */ diff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c index 0c8e58dd5f..96d1bd6724 100644 --- a/tests/qtest/pnv-phb4-test.c +++ b/tests/qtest/pnv-phb4-test.c @@ -139,6 +139,12 @@ static void phb4_writeonly_read_test(QTestState *qts) g_assert_cmpuint(val, ==, 0x0); } +/* Check that reading an unimplemented address 0x0 returns -1 */ +static void phb4_unimplemented_read_test(QTestState *qts) +{ + g_assert_cmpint(pnv_phb4_xscom_read(qts, 0x0), ==, -1); +} + static void test_phb4(void) { QTestState *qts = NULL; @@ -157,6 +163,9 @@ static void test_phb4(void) /* Check write-only logic */ phb4_writeonly_read_test(qts); + /* Check unimplemented register read */ + phb4_unimplemented_read_test(qts); + qtest_quit(qts); } From patchwork Thu Mar 21 10:04:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Saif Abrar X-Patchwork-Id: 1914353 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=V40yFl0U; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4V0h2Z44Fnz1yWy for ; Thu, 21 Mar 2024 21:07:02 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnFIN-00074v-Se; Thu, 21 Mar 2024 06:05:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFI6-0006zd-Ll; Thu, 21 Mar 2024 06:04:55 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFI4-0007Ze-G4; Thu, 21 Mar 2024 06:04:54 -0400 Received: from pps.filterd (m0360072.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 42L9xBBe013186; Thu, 21 Mar 2024 10:04:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=JWY/5JQscLnibOBNvGRcu3fooQXwmOdt9anVI32r2zc=; b=V40yFl0UHPXuT43KXk4kRxhBmoxqQm0vpyNcqMYSmdZInt3q/ZToA+5gbta/R8VcoruW xLkH/e1786AWfJzOxTCm9Y2V05yOB0kv72Tq910+377/e2KQ7wnx6BRncmMzSAh0a0Lu Wj4Np1Qvjz5ghUqd8IOpd50HtYluUDgNqR6bJe/bmEMJ4TY8ergl8AujVOZg+MxeZ24V CkypyEFoTGfF4opyz4QysPokn6P9fyFOXT7jE3KF/Sg70dVBr7FeSQ3D26C/StsMJwZJ YzJEbKru+v0ojcFY62eY87c3+bMCvXb/3UDZwQFAELnLOhmRNCLhj2arfbp5k4VGf57B qw== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0g5hgcnp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:43 +0000 Received: from m0360072.ppops.net (m0360072.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 42LA4RBE022934; Thu, 21 Mar 2024 10:04:43 GMT Received: from ppma12.dal12v.mail.ibm.com (dc.9e.1632.ip4.static.sl-reverse.com [50.22.158.220]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0g5hgcnk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:43 +0000 Received: from pps.filterd (ppma12.dal12v.mail.ibm.com [127.0.0.1]) by ppma12.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 42L8vEnE017242; Thu, 21 Mar 2024 10:04:42 GMT Received: from smtprelay03.wdc07v.mail.ibm.com ([172.16.1.70]) by ppma12.dal12v.mail.ibm.com (PPS) with ESMTPS id 3wwnrtmh81-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:42 +0000 Received: from smtpav04.dal12v.mail.ibm.com (smtpav04.dal12v.mail.ibm.com [10.241.53.103]) by smtprelay03.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 42LA4cYu24773156 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 21 Mar 2024 10:04:41 GMT Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CF4D25806F; Thu, 21 Mar 2024 10:04:36 +0000 (GMT) Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5DACB58067; Thu, 21 Mar 2024 10:04:36 +0000 (GMT) Received: from gfwr516.rchland.ibm.com (unknown [9.10.239.105]) by smtpav04.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 21 Mar 2024 10:04:36 +0000 (GMT) From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH 06/10] pnv/phb4: Set link-active status in HPSTAT and LMR registers Date: Thu, 21 Mar 2024 05:04:18 -0500 Message-Id: <20240321100422.5347-7-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> References: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: anYM_SM5mCyoCkn9hi5L2V8cdpVytosh X-Proofpoint-ORIG-GUID: 6Lu9-zAwNhJck7uhguMn11vN7xpz5KUP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-21_06,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 mlxlogscore=999 bulkscore=0 adultscore=0 mlxscore=0 suspectscore=0 impostorscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2403140000 definitions=main-2403210069 Received-SPF: none client-ip=148.163.158.5; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Config-read the link-status register in the PCI-E macro, Depending on the link-active bit, set the link-active status in the HOTPLUG_STATUS and LINK_MANAGEMENT registers Also, clear the Presence-status active low bit in HOTPLUG_STATUS reg after config-reading the slot-status in the PCI-E macro. Signed-off-by: Saif Abrar --- hw/pci-host/pnv_phb4.c | 57 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 4e3a6b37f9..7b3d75bae6 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -516,6 +516,19 @@ static uint32_t get_exp_offset(PnvPHB4 *phb) return rpc->exp_offset; } +/* + * Config-read the link-status register in the PCI-E macro, + * convert to LE and check the link-active bit. + */ +static uint32_t is_link_active(PnvPHB4 *phb) +{ + uint32_t exp_offset = get_exp_offset(phb); + + return (bswap32(pnv_phb4_rc_config_read(phb, + exp_offset + PCI_EXP_LNKSTA, 4)) + & PCI_EXP_LNKSTA_DLLLA); +} + #define RC_CONFIG_WRITE(a, v) pnv_phb4_rc_config_write(phb, a, 4, v) /* @@ -757,6 +770,11 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, val = 0; break; + case PHB_PCIE_HOTPLUG_STATUS: + /* For normal operations, Simspeed diagnostic bit is always zero */ + val &= PHB_PCIE_HPSTAT_SIMDIAG; + break; + /* Read only registers */ case PHB_CPU_LOADSTORE_STATUS: case PHB_ETU_ERR_SUMMARY: @@ -968,8 +986,40 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) val |= PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT; return val; + /* + * Read PCI-E registers and set status for: + * - Card present (active low bit 10) + * - Link active (bit 12) + */ case PHB_PCIE_HOTPLUG_STATUS: - /* Clear write-only bit */ + /* + * Presence-status bit hpi_present_n is active-low, with reset value 1. + * Start by setting this bit to 1, indicating the card is not present. + * Then check the PCI-E register and clear the bit if card is present. + */ + val |= PHB_PCIE_HPSTAT_PRESENCE; + + /* Get the PCI-E capability offset from the root-port */ + uint32_t exp_base = get_exp_offset(phb); + + /* + * Config-read the PCI-E macro register for slot-status. + * Method for config-read converts to BE value. + * To check actual bit in the PCI-E register, + * convert the value back to LE using bswap32(). + * Clear the Presence-status active low bit. + */ + if (bswap32(pnv_phb4_rc_config_read(phb, exp_base + PCI_EXP_SLTSTA, 4)) + & PCI_EXP_SLTSTA_PDS) { + val &= ~PHB_PCIE_HPSTAT_PRESENCE; + } + + /* Check if link is active and set the bit */ + if (is_link_active(phb)) { + val |= PHB_PCIE_HPSTAT_LINKACTIVE; + } + + /* Clear write-only resample-bit */ val &= ~PHB_PCIE_HPSTAT_RESAMPLE; return val; @@ -977,6 +1027,11 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) case PHB_PCIE_LMR: /* These write-only bits always read as 0 */ val &= ~(PHB_PCIE_LMR_CHANGELW | PHB_PCIE_LMR_RETRAINLINK); + + /* Check if link is active and set the bit */ + if (is_link_active(phb)) { + val |= PHB_PCIE_LMR_LINKACTIVE; + } return val; /* Silent simple reads */ From patchwork Thu Mar 21 10:04:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Saif Abrar X-Patchwork-Id: 1914339 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=ZHU4TUhq; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4V0h1C1Ry5z1yWy for ; Thu, 21 Mar 2024 21:05:51 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnFI4-0006yr-DD; Thu, 21 Mar 2024 06:04:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFI3-0006yT-O2; Thu, 21 Mar 2024 06:04:51 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFI2-0007ZG-6u; Thu, 21 Mar 2024 06:04:51 -0400 Received: from pps.filterd (m0353722.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 42L8xj1x019472; Thu, 21 Mar 2024 10:04:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=5Pru400Bab22YQoPrfRbBsv6HdwOVVwOb1Gr3mkgcIc=; b=ZHU4TUhqH3BvqRjbBQtGKLxiLd/P3KINCvCYWQrdVgtClwL8EBNIFjQ6Vr3oSDBJFeSM 6ErJ7QVdpP1Utgdztj4YSQEzJKKm11HX5cRWWLTUfVFlCjBLND19BPbofVvxsjbSkjvz 9zseONAUL6wr0rCyOB0XHdPwVuHiJY130xGfBiKFkeA32OxZkeATv8DHbBO9e92Gm2fr 5jtUSX4MlWPtA59hMBsmDOZ8dUhijm29PKsXFN8horqomYIzXpk55rAwA1JK8/Y2mgwO aSaoo/iXxKUukPODz2wFJcNt+oWSCFawzitfcbusyJwbHJBS+wX8OUoEhW1ZLgbNE4mq cw== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0hve85f0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:41 +0000 Received: from m0353722.ppops.net (m0353722.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 42LA4fvX015044; Thu, 21 Mar 2024 10:04:41 GMT Received: from ppma22.wdc07v.mail.ibm.com (5c.69.3da9.ip4.static.sl-reverse.com [169.61.105.92]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0hve85ev-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:41 +0000 Received: from pps.filterd (ppma22.wdc07v.mail.ibm.com [127.0.0.1]) by ppma22.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 42L989Fu015807; Thu, 21 Mar 2024 10:04:40 GMT Received: from smtprelay04.wdc07v.mail.ibm.com ([172.16.1.71]) by ppma22.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3wwp50cfk8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:40 +0000 Received: from smtpav04.dal12v.mail.ibm.com (smtpav04.dal12v.mail.ibm.com [10.241.53.103]) by smtprelay04.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 42LA4bJ358065278 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 21 Mar 2024 10:04:39 GMT Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5A9C058064; Thu, 21 Mar 2024 10:04:37 +0000 (GMT) Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DD1F758069; Thu, 21 Mar 2024 10:04:36 +0000 (GMT) Received: from gfwr516.rchland.ibm.com (unknown [9.10.239.105]) by smtpav04.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 21 Mar 2024 10:04:36 +0000 (GMT) From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH 07/10] pnv/phb4: Set link speed and width in the DLP training control register Date: Thu, 21 Mar 2024 05:04:19 -0500 Message-Id: <20240321100422.5347-8-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> References: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: GmeS-rL3pzEFGC2OpPXT7_z_KhECocFa X-Proofpoint-ORIG-GUID: KzlHthrTuVkWM386X7f01Y_cjD7sQNev X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-21_06,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 lowpriorityscore=0 clxscore=1015 bulkscore=0 malwarescore=0 suspectscore=0 impostorscore=0 priorityscore=1501 mlxscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2403140000 definitions=main-2403210069 Received-SPF: none client-ip=148.163.158.5; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Get the current link-status from PCIE macro. Extract link-speed and link-width from the link-status and set in the DLP training control (PCIE_DLP_TCR) register. Signed-off-by: Saif Abrar Reviewed-by: Cédric Le Goater --- hw/pci-host/pnv_phb4.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 7b3d75bae6..6823ffab54 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -980,10 +980,27 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) val |= PHB_PCIE_SCR_PLW_X16; /* RO bit */ break; - /* Link training always appears trained */ case PHB_PCIE_DLP_TRAIN_CTL: - /* TODO: Do something sensible with speed ? */ + /* Link training always appears trained */ val |= PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT; + + /* Get the current link-status from PCIE */ + uint32_t exp_offset = get_exp_offset(phb); + uint32_t lnkstatus = bswap32(pnv_phb4_rc_config_read(phb, + exp_offset + PCI_EXP_LNKSTA, 4)); + + /* Extract link-speed from the link-status */ + uint32_t v = lnkstatus & PCI_EXP_LNKSTA_CLS; + /* Set the current link-speed at the LINK_SPEED position */ + val = SETFIELD(PHB_PCIE_DLP_LINK_SPEED, val, v); + + /* + * Extract link-width from the link-status, + * after shifting the required bitfields. + */ + v = (lnkstatus & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; + /* Set the current link-width at the LINK_WIDTH position */ + val = SETFIELD(PHB_PCIE_DLP_LINK_WIDTH, val, v); return val; /* From patchwork Thu Mar 21 10:04:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Saif Abrar X-Patchwork-Id: 1914341 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=Bc7yfBHv; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4V0h1R67NGz1yWy for ; Thu, 21 Mar 2024 21:06:03 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnFIM-00074J-FF; Thu, 21 Mar 2024 06:05:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFI6-0006zT-EK; Thu, 21 Mar 2024 06:04:54 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFI4-0007ZW-7S; Thu, 21 Mar 2024 06:04:54 -0400 Received: from pps.filterd (m0356517.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 42L6uTsK027483; Thu, 21 Mar 2024 10:04:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=cqfwocoJ1VRJ3akQdBJW5OtfRFQr2bym1G0I+L+Wr24=; b=Bc7yfBHvyNzLAZ0Xbvuo22BWf+STfRi24+Vf0mPNGrw856FTdldeaMfHgfMJLf6QoOY7 6gWrkssityxXTPRTEQMH/lJQNxqSp5tQznQi4FMjUyTQGRntbKhcakWSn5dg49tb8NEl qQG/USHmfqKiQRZjewdfHBQu+UiOUF6XnXSp/wf4XE9SCSaMf9Xa2hKXUEL4PD30WCsb cqsTbreNTICUj3wzorCtAb8RXBfWoyn0nzA0qloOOr9+GEQYG07oh+Cx4gt5Dd8AB5cd x6AIic8iblzxjipXnmbyja5qgeeldC+gQTNGrH3Zs3Jyp7gXv52+YtYmr+pbEM92jg/l 7w== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0e5ugmbj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:43 +0000 Received: from m0356517.ppops.net (m0356517.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 42LA4gmq022498; Thu, 21 Mar 2024 10:04:42 GMT Received: from ppma23.wdc07v.mail.ibm.com (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0e5ugmbg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:42 +0000 Received: from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1]) by ppma23.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 42LA0svw011595; Thu, 21 Mar 2024 10:04:41 GMT Received: from smtprelay04.wdc07v.mail.ibm.com ([172.16.1.71]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3wwq8mc6fm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:41 +0000 Received: from smtpav04.dal12v.mail.ibm.com (smtpav04.dal12v.mail.ibm.com [10.241.53.103]) by smtprelay04.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 42LA4ccQ26542728 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 21 Mar 2024 10:04:40 GMT Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DB7705805A; Thu, 21 Mar 2024 10:04:37 +0000 (GMT) Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 689B858069; Thu, 21 Mar 2024 10:04:37 +0000 (GMT) Received: from gfwr516.rchland.ibm.com (unknown [9.10.239.105]) by smtpav04.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 21 Mar 2024 10:04:37 +0000 (GMT) From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH 08/10] pnv/phb4: Implement IODA PCT table Date: Thu, 21 Mar 2024 05:04:20 -0500 Message-Id: <20240321100422.5347-9-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> References: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: jdc6Ts4V6Zu1M2DMbHZI-X2oDkAmKzy1 X-Proofpoint-GUID: g2yJa05f8mZeEwjFm4_zelYQIjMOEkzd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-21_06,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 suspectscore=0 mlxlogscore=878 spamscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2403140000 definitions=main-2403210069 Received-SPF: none client-ip=148.163.156.1; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org IODA PCT table (#3) is implemented without any functionality, being a debug table. Signed-off-by: Saif Abrar Reviewed-by: Cédric Le Goater --- hw/pci-host/pnv_phb4.c | 6 ++++++ include/hw/pci-host/pnv_phb4.h | 2 ++ include/hw/pci-host/pnv_phb4_regs.h | 1 + 3 files changed, 9 insertions(+) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 6823ffab54..f48750ee54 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -263,6 +263,10 @@ static uint64_t *pnv_phb4_ioda_access(PnvPHB4 *phb, mask = phb->big_phb ? PNV_PHB4_MAX_MIST : (PNV_PHB4_MAX_MIST >> 1); mask -= 1; break; + case IODA3_TBL_PCT: + tptr = phb->ioda_PCT; + mask = 7; + break; case IODA3_TBL_RCAM: mask = phb->big_phb ? 127 : 63; break; @@ -361,6 +365,8 @@ static void pnv_phb4_ioda_write(PnvPHB4 *phb, uint64_t val) /* Handle side effects */ switch (table) { case IODA3_TBL_LIST: + case IODA3_TBL_PCT: + /* No action for debug tables */ break; case IODA3_TBL_MIST: { /* Special mask for MIST partial write */ diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 91e81eee0e..6d83e5616f 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -64,6 +64,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4) #define PNV_PHB4_MAX_LSIs 8 #define PNV_PHB4_MAX_INTs 4096 #define PNV_PHB4_MAX_MIST (PNV_PHB4_MAX_INTs >> 2) +#define PNV_PHB4_MAX_PCT 128 #define PNV_PHB4_MAX_MMIO_WINDOWS 32 #define PNV_PHB4_MIN_MMIO_WINDOWS 16 #define PNV_PHB4_NUM_REGS (0x3000 >> 3) @@ -144,6 +145,7 @@ struct PnvPHB4 { /* On-chip IODA tables */ uint64_t ioda_LIST[PNV_PHB4_MAX_LSIs]; uint64_t ioda_MIST[PNV_PHB4_MAX_MIST]; + uint64_t ioda_PCT[PNV_PHB4_MAX_PCT]; uint64_t ioda_TVT[PNV_PHB4_MAX_TVEs]; uint64_t ioda_MBT[PNV_PHB4_MAX_MBEs]; uint64_t ioda_MDT[PNV_PHB4_MAX_PEs]; diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_phb4_regs.h index c1d5a83271..e30adff7b2 100644 --- a/include/hw/pci-host/pnv_phb4_regs.h +++ b/include/hw/pci-host/pnv_phb4_regs.h @@ -486,6 +486,7 @@ #define IODA3_TBL_LIST 1 #define IODA3_TBL_MIST 2 +#define IODA3_TBL_PCT 3 #define IODA3_TBL_RCAM 5 #define IODA3_TBL_MRT 6 #define IODA3_TBL_PESTA 7 From patchwork Thu Mar 21 10:04:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Saif Abrar X-Patchwork-Id: 1914350 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=XpZ5dhfo; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4V0h2J6CTSz1yWy for ; Thu, 21 Mar 2024 21:06:48 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnFIg-0007Iy-Cj; Thu, 21 Mar 2024 06:05:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFIA-00070R-J9; Thu, 21 Mar 2024 06:04:59 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFI8-0007Yq-VO; Thu, 21 Mar 2024 06:04:58 -0400 Received: from pps.filterd (m0360083.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 42L8xBGN027838; Thu, 21 Mar 2024 10:04:44 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=uANCeZgXqXhB6w96wEupYPLK13hQ3ZQrNGy4uOq33DY=; b=XpZ5dhfoqNCGebqyDNZ4iWUNPyISH2v4+shEhQ70BSGAHUPCJgpTjnbCD9WVLFNjXDK8 Ul2D2ufWM8gx8ksks4dL9qAoQtW+toFTTCw7FDMfGJIrhFY3V1q3aBVQfjn0NOPfwXfu td6JitLI3bxPg+md3CxuVodz1ZnQ7L13JRZZhkHdtaOnHcHQ0HuVjWb59RaxUscBiZfe CqRnEavkIJjstaft8E2QJB4b79PDzScRqzLM8UTZMwJYnHpUgTtbRqcvOyNHz9CVdMC6 a7FcnH2wauRnjduEtBFcCivgmS2dXaTAbr1yUspYZ7gaj4qhANHxHttprZEgBBoG7jWi qw== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0gc80bu8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:43 +0000 Received: from m0360083.ppops.net (m0360083.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 42LA4h38003485; Thu, 21 Mar 2024 10:04:43 GMT Received: from ppma11.dal12v.mail.ibm.com (db.9e.1632.ip4.static.sl-reverse.com [50.22.158.219]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0gc80bu4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:43 +0000 Received: from pps.filterd (ppma11.dal12v.mail.ibm.com [127.0.0.1]) by ppma11.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 42L7jC9T002779; Thu, 21 Mar 2024 10:04:42 GMT Received: from smtprelay05.wdc07v.mail.ibm.com ([172.16.1.72]) by ppma11.dal12v.mail.ibm.com (PPS) with ESMTPS id 3wwrf2uuae-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:42 +0000 Received: from smtpav04.dal12v.mail.ibm.com (smtpav04.dal12v.mail.ibm.com [10.241.53.103]) by smtprelay05.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 42LA4cvP11600542 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 21 Mar 2024 10:04:40 GMT Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6655758066; Thu, 21 Mar 2024 10:04:38 +0000 (GMT) Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E937758069; Thu, 21 Mar 2024 10:04:37 +0000 (GMT) Received: from gfwr516.rchland.ibm.com (unknown [9.10.239.105]) by smtpav04.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 21 Mar 2024 10:04:37 +0000 (GMT) From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH 09/10] hw/pci: Set write-mask bits for PCIE Link-Control-2 register Date: Thu, 21 Mar 2024 05:04:21 -0500 Message-Id: <20240321100422.5347-10-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> References: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 21ry7I3VE5mL2z_iAwIHN4U05MC9bwCd X-Proofpoint-GUID: 1YzBzkFti0jm5hOR5nyfSpxlHwfCy6V7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-21_06,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=773 impostorscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 phishscore=0 mlxscore=0 bulkscore=0 clxscore=1015 adultscore=0 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2403140000 definitions=main-2403210069 Received-SPF: none client-ip=148.163.156.1; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org PHB updates the register PCIE Link-Control-2. Set the write-mask bits for TLS, ENTER_COMP, TX_MARGIN, HASD, MOD_COMP, COMP_SOS and COMP_P_DE. Signed-off-by: Saif Abrar --- hw/pci/pcie.c | 6 ++++++ include/standard-headers/linux/pci_regs.h | 3 +++ 2 files changed, 9 insertions(+) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 4b2f0805c6..e3081f6b84 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -212,6 +212,12 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB); + pci_set_word(dev->wmask + pos + PCI_EXP_LNKCTL2, + PCI_EXP_LNKCTL2_TLS | PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN | PCI_EXP_LNKCTL2_HASD | + PCI_EXP_LNKCTL2_MOD_COMP | PCI_EXP_LNKCTL2_COMP_SOS | + PCI_EXP_LNKCTL2_COMP_P_DE); + if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) { /* read-only to behave like a 'NULL' Extended Capability Header */ pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0); diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h index a39193213f..f743defe91 100644 --- a/include/standard-headers/linux/pci_regs.h +++ b/include/standard-headers/linux/pci_regs.h @@ -694,6 +694,9 @@ #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ #define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */ +#define PCI_EXP_LNKCTL2_MOD_COMP 0x0400 /* Enter Modified Compliance */ +#define PCI_EXP_LNKCTL2_COMP_SOS 0x0800 /* Compliance SOS */ +#define PCI_EXP_LNKCTL2_COMP_P_DE 0xF000 /* Compliance Preset/De-emphasis */ #define PCI_EXP_LNKSTA2 0x32 /* Link Status 2 */ #define PCI_EXP_LNKSTA2_FLIT 0x0400 /* Flit Mode Status */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link */ From patchwork Thu Mar 21 10:04:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Saif Abrar X-Patchwork-Id: 1914355 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=UqOIAg3x; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4V0h2z2Cjsz23rR for ; Thu, 21 Mar 2024 21:07:23 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnFIl-0007SU-SY; Thu, 21 Mar 2024 06:05:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFI9-00070G-C2; Thu, 21 Mar 2024 06:04:58 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnFI6-0007aC-OF; Thu, 21 Mar 2024 06:04:57 -0400 Received: from pps.filterd (m0356516.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 42L3smtY029608; Thu, 21 Mar 2024 10:04:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=JxHbuBfZMHCn/MdB2pMB1m4lPxtIDcYBIvA/2braID4=; b=UqOIAg3xoqg7eze/H0wyFwYDpFQEDC6L/ALgjhbxNX3+Uw5qStZ9DAVbfmIXLSQqmvoZ 6Kg3RRtl3A1WXytJ/LSaW5s4pvXontGKxwvQM4nmakfXHSNhcGVihyDrT2O5DkCpcgT+ MGpNaFj2TQ9ejT6dY30moyjV2EY37ou8rT4d2WNYWd/8DeFcewZwJECv8lRtVI2t/nHJ rJV61hV/2aUL1VaIitN+ysLiHSQ3OK4xsRN6I37hakY/iMsSAlzkZfQE8ggUriWMt9Pv mw2+Oe3865qikxK7fQ6fFu2Zjh1kBHvXwGHuYP4IM77/QlnX3rCd6l/R5yZdMrW0wX8a hA== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0an30x75-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:45 +0000 Received: from m0356516.ppops.net (m0356516.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 42LA4jm2026082; Thu, 21 Mar 2024 10:04:45 GMT Received: from ppma12.dal12v.mail.ibm.com (dc.9e.1632.ip4.static.sl-reverse.com [50.22.158.220]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3x0an30x73-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:45 +0000 Received: from pps.filterd (ppma12.dal12v.mail.ibm.com [127.0.0.1]) by ppma12.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 42L8lLVF017194; Thu, 21 Mar 2024 10:04:44 GMT Received: from smtprelay05.wdc07v.mail.ibm.com ([172.16.1.72]) by ppma12.dal12v.mail.ibm.com (PPS) with ESMTPS id 3wwnrtmh85-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 10:04:44 +0000 Received: from smtpav04.dal12v.mail.ibm.com (smtpav04.dal12v.mail.ibm.com [10.241.53.103]) by smtprelay05.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 42LA4ejx27263510 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 21 Mar 2024 10:04:43 GMT Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E5C1A58062; Thu, 21 Mar 2024 10:04:38 +0000 (GMT) Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7461958067; Thu, 21 Mar 2024 10:04:38 +0000 (GMT) Received: from gfwr516.rchland.ibm.com (unknown [9.10.239.105]) by smtpav04.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 21 Mar 2024 10:04:38 +0000 (GMT) From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH 10/10] pnv/phb4: Mask off LSI Source-ID based on number of interrupts Date: Thu, 21 Mar 2024 05:04:22 -0500 Message-Id: <20240321100422.5347-11-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> References: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: fGjwtFZvLHRwOCdkRUO7BBULAIuKPu0g X-Proofpoint-ORIG-GUID: SVPjCPlUmgfaaLxJH9HAyzfaGA5WJtZg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-21_06,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 mlxscore=0 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2403140000 definitions=main-2403210069 Received-SPF: none client-ip=148.163.158.5; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add a method to reset the value of LSI Source-ID. Mask off LSI source-id based on number of interrupts in the big/small PHB. Signed-off-by: Saif Abrar --- hw/pci-host/pnv_phb4.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index f48750ee54..8fbaf6512e 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -489,6 +489,7 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb) lsi_base = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]); lsi_base <<= 3; + lsi_base &= (xsrc->nr_irqs - 1); /* TODO: handle reset values of PHB_LSI_SRC_ID */ if (!lsi_base) { @@ -1966,6 +1967,12 @@ static void pnv_phb4_ro_mask_init(PnvPHB4 *phb) /* TODO: Add more RO-masks as regs are implemented in the model */ } +static void pnv_phb4_fund_A_reset(PnvPHB4 *phb) +{ + phb->regs[PHB_LSI_SOURCE_ID >> 3] = PPC_BITMASK(4, 12); + pnv_phb4_update_xsrc(phb); +} + static void pnv_phb4_err_reg_reset(PnvPHB4 *phb) { STICKY_RST(PHB_ERR_STATUS, 0, PPC_BITMASK(0, 33)); @@ -2023,6 +2030,7 @@ static void pnv_phb4_reset(void *dev) pnv_phb4_cfg_core_reset(phb); pnv_phb4_pbl_core_reset(phb); + pnv_phb4_fund_A_reset(phb); pnv_phb4_err_reg_reset(phb); pnv_phb4_pcie_stack_reg_reset(phb); pnv_phb4_regb_err_reg_reset(phb); @@ -2102,8 +2110,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp) return; } - pnv_phb4_update_xsrc(phb); - phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs); pnv_phb4_xscom_realize(phb);