diff mbox

[v1,1/1] cadence_gem: Correct Marvell PHY SPCFC reset value

Message ID c795069e49040ff770fe2ece19dfe1791b729e22.1441316450.git.alistair.francis@xilinx.com
State New
Headers show

Commit Message

Alistair Francis Sept. 3, 2015, 10:10 p.m. UTC 
Bit 15 of the PHY Specific Status Register is reserved and
should remain 0. Fix the reset value to ensure that the 15th
bit is not set.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
http://www.marvell.com/transceivers/assets/Marvell-88E3016-Fast-Ethernet.pdf

 hw/net/cadence_gem.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

Comments

Edgar E. Iglesias Sept. 3, 2015, 10:56 p.m. UTC | #1 
On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote:
> Bit 15 of the PHY Specific Status Register is reserved and
> should remain 0. Fix the reset value to ensure that the 15th
> bit is not set.
> 
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>


> ---
> http://www.marvell.com/transceivers/assets/Marvell-88E3016-Fast-Ethernet.pdf
> 
>  hw/net/cadence_gem.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 494a346..1127223 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -951,7 +951,7 @@ static void gem_phy_reset(CadenceGEMState *s)
>      s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00;
>      s->phy_regs[PHY_REG_EXTSTAT] = 0x3000;
>      s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078;
> -    s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0xBC00;
> +    s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00;
>      s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60;
>      s->phy_regs[PHY_REG_LED] = 0x4100;
>      s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A;
> -- 
> 1.7.1
>
Alistair Francis Sept. 4, 2015, 6 p.m. UTC | #2 
On Thu, Sep 3, 2015 at 3:56 PM, Edgar E. Iglesias
<edgar.iglesias@xilinx.com> wrote:
> On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote:
>> Bit 15 of the PHY Specific Status Register is reserved and
>> should remain 0. Fix the reset value to ensure that the 15th
>> bit is not set.
>>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>
> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Thanks Edgar.

Should this go via the ARM queue?

Thanks,

Alistair

>
>
>> ---
>> http://www.marvell.com/transceivers/assets/Marvell-88E3016-Fast-Ethernet.pdf
>>
>>  hw/net/cadence_gem.c |    2 +-
>>  1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
>> index 494a346..1127223 100644
>> --- a/hw/net/cadence_gem.c
>> +++ b/hw/net/cadence_gem.c
>> @@ -951,7 +951,7 @@ static void gem_phy_reset(CadenceGEMState *s)
>>      s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00;
>>      s->phy_regs[PHY_REG_EXTSTAT] = 0x3000;
>>      s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078;
>> -    s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0xBC00;
>> +    s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00;
>>      s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60;
>>      s->phy_regs[PHY_REG_LED] = 0x4100;
>>      s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A;
>> --
>> 1.7.1
>>
>
Peter Maydell Sept. 4, 2015, 6:12 p.m. UTC | #3 
On 4 September 2015 at 19:00, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> On Thu, Sep 3, 2015 at 3:56 PM, Edgar E. Iglesias
> <edgar.iglesias@xilinx.com> wrote:
>> On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote:
>>> Bit 15 of the PHY Specific Status Register is reserved and
>>> should remain 0. Fix the reset value to ensure that the 15th
>>> bit is not set.
>>>
>>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>>
>> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> Thanks Edgar.
>
> Should this go via the ARM queue?

I was planning to pick it up, unless Edgar would rather
something else.

-- PMM
Alistair Francis Sept. 4, 2015, 6:32 p.m. UTC | #4 
On Fri, Sep 4, 2015 at 11:12 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 4 September 2015 at 19:00, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
>> On Thu, Sep 3, 2015 at 3:56 PM, Edgar E. Iglesias
>> <edgar.iglesias@xilinx.com> wrote:
>>> On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote:
>>>> Bit 15 of the PHY Specific Status Register is reserved and
>>>> should remain 0. Fix the reset value to ensure that the 15th
>>>> bit is not set.
>>>>
>>>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>>>
>>> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>>
>> Thanks Edgar.
>>
>> Should this go via the ARM queue?
>
> I was planning to pick it up, unless Edgar would rather
> something else.

Great! Thanks Peter.

That's fine with me, just thought I would check.

Thanks,

Alistair

>
> -- PMM
>
Edgar E. Iglesias Sept. 4, 2015, 9:08 p.m. UTC | #5 
On Fri, Sep 04, 2015 at 07:12:23PM +0100, Peter Maydell wrote:
> On 4 September 2015 at 19:00, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
> > On Thu, Sep 3, 2015 at 3:56 PM, Edgar E. Iglesias
> > <edgar.iglesias@xilinx.com> wrote:
> >> On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote:
> >>> Bit 15 of the PHY Specific Status Register is reserved and
> >>> should remain 0. Fix the reset value to ensure that the 15th
> >>> bit is not set.
> >>>
> >>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> >>
> >> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> >
> > Thanks Edgar.
> >
> > Should this go via the ARM queue?
> 
> I was planning to pick it up, unless Edgar would rather
> something else.

Sounds good if you take it Peter, thanks!

Best regards,
Edgar
Peter Maydell Sept. 8, 2015, 2:51 p.m. UTC | #6 
On 3 September 2015 at 23:10, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> Bit 15 of the PHY Specific Status Register is reserved and
> should remain 0. Fix the reset value to ensure that the 15th
> bit is not set.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> http://www.marvell.com/transceivers/assets/Marvell-88E3016-Fast-Ethernet.pdf
>
>  hw/net/cadence_gem.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 494a346..1127223 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -951,7 +951,7 @@ static void gem_phy_reset(CadenceGEMState *s)
>      s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00;
>      s->phy_regs[PHY_REG_EXTSTAT] = 0x3000;
>      s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078;
> -    s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0xBC00;
> +    s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00;
>      s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60;
>      s->phy_regs[PHY_REG_LED] = 0x4100;
>      s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A;


Applied to target-arm.next, thanks.

-- PMM
diff mbox

Patch

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 494a346..1127223 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -951,7 +951,7 @@  static void gem_phy_reset(CadenceGEMState *s)
     s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00;
     s->phy_regs[PHY_REG_EXTSTAT] = 0x3000;
     s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078;
-    s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0xBC00;
+    s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00;
     s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60;
     s->phy_regs[PHY_REG_LED] = 0x4100;
     s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A;