Show patches with: Submitter = Peter Maydell       |    State = Action Required       |    Archived = No       |   9529 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v2] qemu-ga: Convert invocation documentation to rST [v2] qemu-ga: Convert invocation documentation to rST - - 1 1 0 0 0 2019-06-18 Peter Maydell New
[6/6] target/arm: Execute Thumb instructions when their condbits are 0xf Six minor M-profile bugfixes - - 1 - 0 0 0 2019-06-17 Peter Maydell New
[5/6] hw/timer/armv7m_systick: Forbid non-privileged accesses Six minor M-profile bugfixes - - 2 - 0 0 0 2019-06-17 Peter Maydell New
[4/6] target/arm: Use _ra versions of cpu_stl_data() in v7M helpers Six minor M-profile bugfixes - - 1 - 0 0 0 2019-06-17 Peter Maydell New
[3/6] target/arm: v8M: Check state of exception being returned from Six minor M-profile bugfixes - - 1 - 0 0 0 2019-06-17 Peter Maydell New
[2/6] arm v8M: Forcibly clear negative-priority exceptions on deactivate Six minor M-profile bugfixes - - 1 - 0 0 0 2019-06-17 Peter Maydell New
[1/6] target/arm: NS BusFault on vector table fetch escalates to NS HardFault Six minor M-profile bugfixes - - - - 0 0 0 2019-06-17 Peter Maydell New
target/arm: Check for dp support for dp VFM, not sp target/arm: Check for dp support for dp VFM, not sp - - 1 - 0 0 0 2019-06-17 Peter Maydell New
[PULL,4/4] docs: Build and install specs manual [PULL,1/4] Convert "translator internals" docs to RST, move to devel manual 1 - - - 0 0 0 2019-06-17 Peter Maydell New
[PULL,3/4] docs/specs/index.rst: Fix minor syntax issues [PULL,1/4] Convert "translator internals" docs to RST, move to devel manual 1 - 1 - 0 0 0 2019-06-17 Peter Maydell New
[PULL,2/4] qemu-tech.texi: Remove "QEMU compared to other emulators" section [PULL,1/4] Convert "translator internals" docs to RST, move to devel manual 1 - 2 - 0 0 0 2019-06-17 Peter Maydell New
[PULL,1/4] Convert "translator internals" docs to RST, move to devel manual [PULL,1/4] Convert "translator internals" docs to RST, move to devel manual 1 - 1 - 0 0 0 2019-06-17 Peter Maydell New
[PULL,0/4] docs queue - - - - 0 0 0 2019-06-17 Peter Maydell New
[PULL,24/24] target/arm: Only implement doubles if the FPU supports them [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 - 0 0 0 2019-06-17 Peter Maydell New
[PULL,23/24] target/arm: Fix typos in trans function prototypes [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 - 0 0 0 2019-06-17 Peter Maydell New
[PULL,22/24] target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 1 0 0 0 2019-06-17 Peter Maydell New
[PULL,21/24] target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16 [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 1 0 0 0 2019-06-17 Peter Maydell New
[PULL,20/24] target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32 [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 1 0 0 0 2019-06-17 Peter Maydell New
[PULL,19/24] target/arm: Stop using cpu_F0s in Neon VCVT fixed-point ops [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 1 0 0 0 2019-06-17 Peter Maydell New
[PULL,18/24] target/arm: Stop using cpu_F0s for Neon f32/s32 VCVT [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 1 0 0 0 2019-06-17 Peter Maydell New
[PULL,17/24] target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 1 0 0 0 2019-06-17 Peter Maydell New
[PULL,16/24] target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US] [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 1 0 0 0 2019-06-17 Peter Maydell New
[PULL,15/24] target/arm: Stop using cpu_F0s for NEON_2RM_VRINT* [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 1 0 0 0 2019-06-17 Peter Maydell New
[PULL,14/24] target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 1 0 0 0 2019-06-17 Peter Maydell New
[PULL,13/24] target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 1 0 0 0 2019-06-17 Peter Maydell New
[PULL,12/24] target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 1 0 0 0 2019-06-17 Peter Maydell New
[PULL,11/24] target/arm: Move vfp_expand_imm() to translate.[ch] [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 1 0 0 0 2019-06-17 Peter Maydell New
[PULL,10/24] hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1 [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - - - 0 0 0 2019-06-17 Peter Maydell New
[PULL,09/24] hw/intc/arm_gicv3: Fix decoding of ID register range [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 - 0 0 0 2019-06-17 Peter Maydell New
[PULL,08/24] hw/arm: Correctly disable FPU/DSP for some ARMSSE-based boards [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 - 0 0 0 2019-06-17 Peter Maydell New
[PULL,07/24] hw/arm/armv7m: Forward "vfp" and "dsp" properties to CPU [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 2 - 0 0 0 2019-06-17 Peter Maydell New
[PULL,06/24] target/arm: Allow M-profile CPUs to disable the DSP extension via CPU property [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 2 - 0 0 0 2019-06-17 Peter Maydell New
[PULL,05/24] target/arm: Allow VFP and Neon to be disabled via a CPU property [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 2 - 0 0 0 2019-06-17 Peter Maydell New
[PULL,04/24] hw/arm/boot: Honour image size field in AArch64 Image format kernels [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - 1 2 1 0 0 0 2019-06-17 Peter Maydell New
[PULL,03/24] hw/arm/boot: Avoid placing the initrd on top of the kernel [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 1 0 0 0 2019-06-17 Peter Maydell New
[PULL,02/24] hw/arm/boot: Diagnose layouts that put initrd or DTB off the end of RAM [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 1 0 0 0 2019-06-17 Peter Maydell New
[PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero [PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero - - 1 1 0 0 0 2019-06-17 Peter Maydell New
[PULL,00/24] target-arm queue - - - - 0 0 0 2019-06-17 Peter Maydell New
[2/2] target/arm: Only implement doubles if the FPU supports them target/arm: Support single-precision only FPUs - - 1 - 0 0 0 2019-06-14 Peter Maydell New
[1/2] target/arm: Fix typos in trans function prototypes target/arm: Support single-precision only FPUs - - 1 - 0 0 0 2019-06-14 Peter Maydell New
[12/12] target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d target/arm: VFP decodetree conversion followups - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[11/12] target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16 target/arm: VFP decodetree conversion followups - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[10/12] target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32 target/arm: VFP decodetree conversion followups - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[09/12] target/arm: Stop using cpu_F0s in Neon VCVT fixed-point ops target/arm: VFP decodetree conversion followups - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[08/12] target/arm: Stop using cpu_F0s for Neon f32/s32 VCVT target/arm: VFP decodetree conversion followups - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[07/12] target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F target/arm: VFP decodetree conversion followups - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[06/12] target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US] target/arm: VFP decodetree conversion followups - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[05/12] target/arm: Stop using cpu_F0s for NEON_2RM_VRINT* target/arm: VFP decodetree conversion followups - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[04/12] target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F target/arm: VFP decodetree conversion followups - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[03/12] target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F target/arm: VFP decodetree conversion followups - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[02/12] target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm target/arm: VFP decodetree conversion followups - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[01/12] target/arm: Move vfp_expand_imm() to translate.[ch] target/arm: VFP decodetree conversion followups - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[RISU] arm.risu: Avoid VTRN with Vd == Vm [RISU] arm.risu: Avoid VTRN with Vd == Vm - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,v2,00/47] target-arm queue - - - - 0 0 0 2019-06-13 Peter Maydell New
[PULL,48/48] target/arm: Fix short-vector increment behaviour [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,47/48] target/arm: Convert float-to-integer VCVT insns to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,46/48] target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,45/48] target/arm: Convert VJCVT to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,44/48] target/arm: Convert integer-to-float insns to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,43/48] target/arm: Convert double-single precision conversion insns to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,42/48] target/arm: Convert VFP round insns to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,41/48] target/arm: Convert the VCVT-to-f16 insns to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,40/48] target/arm: Convert the VCVT-from-f16 insns to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,39/48] target/arm: Convert VFP comparison insns to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,38/48] target/arm: Convert VMOV (register) to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,37/48] target/arm: Convert VSQRT to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,36/48] target/arm: Convert VNEG to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,35/48] target/arm: Convert VABS to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,34/48] target/arm: Convert VMOV (imm) to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,33/48] target/arm: Convert VFP fused multiply-add insns to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,32/48] target/arm: Convert VDIV to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,31/48] target/arm: Convert VSUB to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,30/48] target/arm: Convert VADD to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,29/48] target/arm: Convert VNMUL to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,28/48] target/arm: Convert VMUL to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,27/48] target/arm: Convert VFP VNMLA to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,26/48] target/arm: Convert VFP VNMLS to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,25/48] target/arm: Convert VFP VMLS to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,24/48] target/arm: Convert VFP VMLA to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,23/48] target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,22/48] target/arm: Convert the VFP load/store multiple insns to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,21/48] target/arm: Convert VFP VLDR and VSTR to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,20/48] target/arm: Convert VFP two-register transfer insns to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,19/48] target/arm: Convert "single-precision" register moves to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,18/48] target/arm: Convert "double-precision" register moves to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,17/48] target/arm: Add helpers for VFP register loads and stores [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,16/48] target/arm: Move the VFP trans_* functions to translate-vfp.inc.c [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,15/48] target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,14/48] target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - - - 0 0 0 2019-06-13 Peter Maydell New
[PULL,13/48] target/arm: Convert VMINNM, VMAXNM to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,12/48] target/arm: Convert the VSEL instructions to decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,11/48] target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,10/48] target/arm: Fix Cortex-R5F MVFR values [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,09/48] target/arm: Factor out VFP access checking code [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,08/48] target/arm: Add stubs for AArch32 VFP decodetree [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,07/48] decodetree: Fix comparison of Field [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 2 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,06/48] target/arm: Fix output of PAuth Auth Untitled series #113574 - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,05/48] hw/core/bus.c: Only the main system bus can have no parent [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 3 1 0 0 0 2019-06-13 Peter Maydell New
[PULL,04/48] hw/arm/smmuv3: Fix decoding of ID register range [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
[PULL,03/48] target/arm: Implement NSACR gating of floating point [PULL,01/48] target/arm: Vectorize USHL and SSHL - - 1 - 0 0 0 2019-06-13 Peter Maydell New
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