| Message ID | 20240528024328.246965-1-alistair.francis@wdc.com |
|---|---|
| State | New |
| Headers | show |
On 5/27/24 19:43, Alistair Francis wrote: > The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946: > > Merge tag 'pull-error-2024-05-27' ofhttps://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700) > > are available in the Git repository at: > > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528 > > for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393: > > target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000) > > ---------------------------------------------------------------- > RISC-V PR for 9.1 > > * APLICs add child earlier than realize > * Fix exposure of Zkr > * Raise exceptions on wrs.nto > * Implement SBI debug console (DBCN) calls for KVM > * Support 64-bit addresses for initrd > * Change RISCV_EXCP_SEMIHOST exception number to 63 > * Tolerate KVM disable ext errors > * Set tval in breakpoints > * Add support for Zve32x extension > * Add support for Zve64x extension > * Relax vector register check in RISCV gdbstub > * Fix the element agnostic Vector function problem > * Fix Zvkb extension config > * Implement dynamic establishment of custom decoder > * Add th.sxstatus CSR emulation > * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions > * Check single width operator for vector fp widen instructions > * Check single width operator for vfncvt.rod.f.f.w > * Remove redudant SEW checking for vector fp narrow/widen instructions > * Prioritize pmp errors in raise_mmu_exception() > * Do not set mtval2 for non guest-page faults > * Remove experimental prefix from "B" extension > * Fixup CBO extension register calculation > * Fix the hart bit setting of AIA > * Fix reg_width in ricsv_gen_dynamic_vector_feature() > * Decode all of the pmpcfg and pmpaddr CSRs > * Raise an exception when CSRRS/CSRRC writes a read-only CSR Fails testing: https://gitlab.com/qemu-project/qemu/-/jobs/6953349448 ERROR:../tests/plugin/insn.c:58:vcpu_init: assertion failed: (count > 0) timeout: the monitored command dumped core Aborted make[1]: *** [Makefile:178: run-plugin-catch-syscalls-with-libinsn.so] Error 134 make: *** [/builds/qemu-project/qemu/tests/Makefile.include:56: run-tcg-tests-riscv64-linux-user] Error 2 #0 riscv_gdb_get_csr (cs=<optimized out>, buf=0x5555558e7f50, n=3072) at ../src/target/riscv/gdbstub.c:183 #1 0x00007ffff7fb7841 in vcpu_init (id=<optimized out>, vcpu_index=<optimized out>) at ../src/tests/plugin/insn.c:57 #2 0x000055555569ef1a in plugin_vcpu_cb__simple (cpu=0x5555558fb820, ev=<optimized out>) at ../src/plugins/core.c:111 After 182 result = riscv_csrrw_debug(env, n, &val, 0, 0); result == 2. r~
The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946: Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528 for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393: target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000) ---------------------------------------------------------------- RISC-V PR for 9.1 * APLICs add child earlier than realize * Fix exposure of Zkr * Raise exceptions on wrs.nto * Implement SBI debug console (DBCN) calls for KVM * Support 64-bit addresses for initrd * Change RISCV_EXCP_SEMIHOST exception number to 63 * Tolerate KVM disable ext errors * Set tval in breakpoints * Add support for Zve32x extension * Add support for Zve64x extension * Relax vector register check in RISCV gdbstub * Fix the element agnostic Vector function problem * Fix Zvkb extension config * Implement dynamic establishment of custom decoder * Add th.sxstatus CSR emulation * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions * Check single width operator for vector fp widen instructions * Check single width operator for vfncvt.rod.f.f.w * Remove redudant SEW checking for vector fp narrow/widen instructions * Prioritize pmp errors in raise_mmu_exception() * Do not set mtval2 for non guest-page faults * Remove experimental prefix from "B" extension * Fixup CBO extension register calculation * Fix the hart bit setting of AIA * Fix reg_width in ricsv_gen_dynamic_vector_feature() * Decode all of the pmpcfg and pmpaddr CSRs * Raise an exception when CSRRS/CSRRC writes a read-only CSR ---------------------------------------------------------------- Alexei Filippov (1): target/riscv: do not set mtval2 for non guest-page faults Alistair Francis (2): target/riscv: rvzicbo: Fixup CBO extension register calculation disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs Andrew Jones (2): target/riscv/kvm: Fix exposure of Zkr target/riscv: Raise exceptions on wrs.nto Cheng Yang (1): hw/riscv/boot.c: Support 64-bit address for initrd Christoph Müllner (1): riscv: thead: Add th.sxstatus CSR emulation Clément Léger (1): target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63 Daniel Henrique Barboza (6): target/riscv/kvm: implement SBI debug console (DBCN) calls target/riscv/kvm: tolerate KVM disable ext errors target/riscv/debug: set tval=pc in breakpoint exceptions trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint target/riscv: prioritize pmp errors in raise_mmu_exception() riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature() Huang Tao (2): target/riscv: Fix the element agnostic function problem target/riscv: Implement dynamic establishment of custom decoder Jason Chien (3): target/riscv: Add support for Zve32x extension target/riscv: Add support for Zve64x extension target/riscv: Relax vector register check in RISCV gdbstub Max Chou (4): target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions target/riscv: rvv: Check single width operator for vector fp widen instructions target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions Rob Bradford (1): target/riscv: Remove experimental prefix from "B" extension Yangyu Chen (1): target/riscv/cpu.c: fix Zvkb extension config Yong-Xuan Wang (1): target/riscv/kvm.c: Fix the hart bit setting of AIA Yu-Ming Chang (1): target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR yang.zhang (1): hw/intc/riscv_aplic: APLICs should add child earlier than realize MAINTAINERS | 1 + target/riscv/cpu.h | 11 ++ target/riscv/cpu_bits.h | 2 +- target/riscv/cpu_cfg.h | 2 + target/riscv/helper.h | 1 + target/riscv/sbi_ecall_interface.h | 17 +++ target/riscv/tcg/tcg-cpu.h | 15 +++ disas/riscv.c | 65 +++++++++- hw/intc/riscv_aplic.c | 8 +- hw/riscv/boot.c | 4 +- target/riscv/cpu.c | 10 +- target/riscv/cpu_helper.c | 37 +++--- target/riscv/csr.c | 71 +++++++++-- target/riscv/debug.c | 3 + target/riscv/gdbstub.c | 8 +- target/riscv/kvm/kvm-cpu.c | 157 ++++++++++++++++++++++++- target/riscv/op_helper.c | 17 ++- target/riscv/tcg/tcg-cpu.c | 50 +++++--- target/riscv/th_csr.c | 79 +++++++++++++ target/riscv/translate.c | 31 +++-- target/riscv/vector_internals.c | 22 ++++ target/riscv/insn_trans/trans_privileged.c.inc | 2 + target/riscv/insn_trans/trans_rvv.c.inc | 46 +++++--- target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 +++-- target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++- target/riscv/meson.build | 1 + 26 files changed, 596 insertions(+), 109 deletions(-) create mode 100644 target/riscv/th_csr.c