| Message ID | 20240516123336.63534-1-jerry.zhangjian@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: zvbb implies zvkb | expand |
Reviewed-by: Frank Chang <frank.chang@sifive.com> On Thu, May 16, 2024 at 8:34 PM Jerry Zhang Jian <jerry.zhangjian@sifive.com> wrote: > - According to RISC-V crypto spec, Zvkb extension is a proper subset of > the Zvbb extension. > > - Reference: > https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10 > > Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> > --- > target/riscv/tcg/tcg-cpu.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 40054a391a..f1a1306ab2 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -658,6 +658,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, > Error **errp) > cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); > } > > + if (cpu->cfg.ext_zvbb) { > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); > + } > + > /* > * In principle Zve*x would also suffice here, were they supported > * in qemu > -- > 2.42.0 > >
On Thu, May 16, 2024 at 10:35 PM Jerry Zhang Jian <jerry.zhangjian@sifive.com> wrote: > > - According to RISC-V crypto spec, Zvkb extension is a proper subset of the Zvbb extension. > > - Reference: https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10 > > Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/tcg/tcg-cpu.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 40054a391a..f1a1306ab2 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -658,6 +658,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); > } > > + if (cpu->cfg.ext_zvbb) { > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); > + } > + > /* > * In principle Zve*x would also suffice here, were they supported > * in qemu > -- > 2.42.0 > >
On Thu, May 16, 2024 at 10:35 PM Jerry Zhang Jian <jerry.zhangjian@sifive.com> wrote: > > - According to RISC-V crypto spec, Zvkb extension is a proper subset of the Zvbb extension. > > - Reference: https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10 > > Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Do you mind rebasing on https://github.com/alistair23/qemu/tree/riscv-to-apply.next? Alistair > --- > target/riscv/tcg/tcg-cpu.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 40054a391a..f1a1306ab2 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -658,6 +658,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); > } > > + if (cpu->cfg.ext_zvbb) { > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); > + } > + > /* > * In principle Zve*x would also suffice here, were they supported > * in qemu > -- > 2.42.0 > >
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Sorry, I had the bad mail client setting. Please ignore the previous email, and I will resubmit the patch. -- Jerry Jerry ZJ <jerry.zhangjian@sifive.com> 於 2024年5月28日 週二 下午8:12寫道： > > *Canary Mail You've received a secure email* > jerry.zhangjian@sifive.com has sent you a secure email via Canary Mail. > Read Secure Email > <https://secure.canarymail.io/read?obj_id=04c03de7-d745-472e-b026-7dd839bc34a0&obj_key=eGJUOWtORkFXenBvWTJyMSt4VGpWdz09&thr_id=04c03de7-d745-472e-b026-7dd839bc34a0> > If you expect to correspond often with jerry.zhangjian@sifive.com, we > recommend you download Canary Mail for free. > Download Canary <https://canarymail.io> > [image: Twitter] <http://www.twitter.com/CanaryMailApp> > [image: Website] <https://canarymail.io> > Privacy <https://canarymail.io/privacy.html> | Terms > <https://canarymail.io/terms.html> | Docs <https://help.canarymail.io/> | > Support <https://canarymail.zendesk.com/hc/en-us/requests/new> > > Copyright © 2021 Canary Mail, All rights reserved. >
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 40054a391a..f1a1306ab2 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -658,6 +658,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); } + if (cpu->cfg.ext_zvbb) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); + } + /* * In principle Zve*x would also suffice here, were they supported * in qemu
- According to RISC-V crypto spec, Zvkb extension is a proper subset of the Zvbb extension. - Reference: https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10 Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> --- target/riscv/tcg/tcg-cpu.c | 4 ++++ 1 file changed, 4 insertions(+)