| Message ID | 20240219082938.238302-1-npiggin@gmail.com |
|---|---|
| State | New |
| Headers | show |
From: Peter Maydell <peter.maydell@linaro.org> The raven_io_ops MemoryRegionOps is the only one in the source tree which sets .valid.unaligned to indicate that it should support unaligned accesses and which does not also set .impl.unaligned to indicate that its read and write functions can do the unaligned handling themselves. This is a problem, because at the moment the core memory system does not implement the support for handling unaligned accesses by doing a series of aligned accesses and combining them (system/memory.c:access_with_adjusted_size() has a TODO comment noting this). Fortunately raven_io_read() and raven_io_write() will correctly deal with the case of being passed an unaligned address, so we can fix the missing unaligned access support by setting .impl.unaligned in the MemoryRegionOps struct. Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region") Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
On Mon, 19 Feb 2024, Nicholas Piggin wrote: > From: Peter Maydell <peter.maydell@linaro.org> > > The raven_io_ops MemoryRegionOps is the only one in the source tree > which sets .valid.unaligned to indicate that it should support > unaligned accesses and which does not also set .impl.unaligned to > indicate that its read and write functions can do the unaligned > handling themselves. This is a problem, because at the moment the > core memory system does not implement the support for handling > unaligned accesses by doing a series of aligned accesses and > combining them (system/memory.c:access_with_adjusted_size() has a > TODO comment noting this). > > Fortunately raven_io_read() and raven_io_write() will correctly deal > with the case of being passed an unaligned address, so we can fix the > missing unaligned access support by setting .impl.unaligned in the > MemoryRegionOps struct. > > Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region") > Reviewed-by: Cédric Le Goater <clg@redhat.com> > Tested-by: Cédric Le Goater <clg@redhat.com> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Hm, this seems to be missing the actual patch. Regards, BALATON Zoltan
On 2/19/24 15:49, BALATON Zoltan wrote: > On Mon, 19 Feb 2024, Nicholas Piggin wrote: >> From: Peter Maydell <peter.maydell@linaro.org> >> >> The raven_io_ops MemoryRegionOps is the only one in the source tree >> which sets .valid.unaligned to indicate that it should support >> unaligned accesses and which does not also set .impl.unaligned to >> indicate that its read and write functions can do the unaligned >> handling themselves. This is a problem, because at the moment the >> core memory system does not implement the support for handling >> unaligned accesses by doing a series of aligned accesses and >> combining them (system/memory.c:access_with_adjusted_size() has a >> TODO comment noting this). >> >> Fortunately raven_io_read() and raven_io_write() will correctly deal >> with the case of being passed an unaligned address, so we can fix the >> missing unaligned access support by setting .impl.unaligned in the >> MemoryRegionOps struct. >> >> Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region") >> Reviewed-by: Cédric Le Goater <clg@redhat.com> >> Tested-by: Cédric Le Goater <clg@redhat.com> >> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> >> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > > Hm, this seems to be missing the actual patch. It's merged already and git knows how to handle this. Thanks, C.
On Mon, 19 Feb 2024 at 14:53, Cédric Le Goater <clg@kaod.org> wrote: > > On 2/19/24 15:49, BALATON Zoltan wrote: > > On Mon, 19 Feb 2024, Nicholas Piggin wrote: > >> From: Peter Maydell <peter.maydell@linaro.org> > >> > >> The raven_io_ops MemoryRegionOps is the only one in the source tree > >> which sets .valid.unaligned to indicate that it should support > >> unaligned accesses and which does not also set .impl.unaligned to > >> indicate that its read and write functions can do the unaligned > >> handling themselves. This is a problem, because at the moment the > >> core memory system does not implement the support for handling > >> unaligned accesses by doing a series of aligned accesses and > >> combining them (system/memory.c:access_with_adjusted_size() has a > >> TODO comment noting this). > >> > >> Fortunately raven_io_read() and raven_io_write() will correctly deal > >> with the case of being passed an unaligned address, so we can fix the > >> missing unaligned access support by setting .impl.unaligned in the > >> MemoryRegionOps struct. > >> > >> Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region") > >> Reviewed-by: Cédric Le Goater <clg@redhat.com> > >> Tested-by: Cédric Le Goater <clg@redhat.com> > >> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > >> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > > > > Hm, this seems to be missing the actual patch. > > It's merged already and git knows how to handle this. Mmm, though this is the result of "rebased onto a tree that already had the commit" rather than "two merges both contain the commit", so we end up with a genuinely empty commit upstream, which is a bit odd looking, though harmless. -- PMM
On 2/19/24 15:55, Peter Maydell wrote: > On Mon, 19 Feb 2024 at 14:53, Cédric Le Goater <clg@kaod.org> wrote: >> >> On 2/19/24 15:49, BALATON Zoltan wrote: >>> On Mon, 19 Feb 2024, Nicholas Piggin wrote: >>>> From: Peter Maydell <peter.maydell@linaro.org> >>>> >>>> The raven_io_ops MemoryRegionOps is the only one in the source tree >>>> which sets .valid.unaligned to indicate that it should support >>>> unaligned accesses and which does not also set .impl.unaligned to >>>> indicate that its read and write functions can do the unaligned >>>> handling themselves. This is a problem, because at the moment the >>>> core memory system does not implement the support for handling >>>> unaligned accesses by doing a series of aligned accesses and >>>> combining them (system/memory.c:access_with_adjusted_size() has a >>>> TODO comment noting this). >>>> >>>> Fortunately raven_io_read() and raven_io_write() will correctly deal >>>> with the case of being passed an unaligned address, so we can fix the >>>> missing unaligned access support by setting .impl.unaligned in the >>>> MemoryRegionOps struct. >>>> >>>> Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region") >>>> Reviewed-by: Cédric Le Goater <clg@redhat.com> >>>> Tested-by: Cédric Le Goater <clg@redhat.com> >>>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> >>>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> >>> >>> Hm, this seems to be missing the actual patch. >> >> It's merged already and git knows how to handle this. > > Mmm, though this is the result of "rebased onto a tree that > already had the commit" rather than "two merges both contain > the commit", so we end up with a genuinely empty commit upstream, > which is a bit odd looking, though harmless. git rebase -i db5f7f9e3ceb and dropping the first patch would cleanup the empty patch. C.
On Mon, 19 Feb 2024 at 08:31, Nicholas Piggin <npiggin@gmail.com> wrote: > > The following changes since commit da96ad4a6a2ef26c83b15fa95e7fceef5147269c: > > Merge tag 'hw-misc-20240215' of https://github.com/philmd/qemu into staging (2024-02-16 11:05:14 +0000) > > are available in the Git repository at: > > https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-9.0-20240219 > > for you to fetch changes up to 922e408e12315121d3e09304b8b8f462ea051af1: > > target/ppc: optimise ppcemb_tlb_t flushing (2024-02-19 18:09:19 +1000) > > ---------------------------------------------------------------- > * Avocado tests for ppc64 to boot FreeBSD, run guests with emulated > or nested hypervisor facilities, among other things. > * Update ppc64 CPU defaults to Power10. > * Add a new powernv10-rainier machine to better capture differences > between the different Power10 systems. > * Implement more device models for powernv. > * 4xx TLB flushing performance and correctness improvements. > * Correct gdb implementation to access some important SPRs. > * Misc cleanups and bug fixes. > > I dropped the BHRB patches, they are very close but minor issue only > noticed recently held them up. Hopefully we can get those and a bunch > of other outstanding submissions in for 9.0 but this PR was taking too > long as it was. > Peter Maydell (1): > hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses Hi Nick -- this commit went upstream via a different route, and so it now appears in this pullrequest as a commit with a commit message but no contents. Could I ask you to respin the pullreq with that commit dropped, please? thanks -- PMM
On Tue Feb 20, 2024 at 3:06 AM AEST, Peter Maydell wrote: > On Mon, 19 Feb 2024 at 08:31, Nicholas Piggin <npiggin@gmail.com> wrote: > > > > The following changes since commit da96ad4a6a2ef26c83b15fa95e7fceef5147269c: > > > > Merge tag 'hw-misc-20240215' of https://github.com/philmd/qemu into staging (2024-02-16 11:05:14 +0000) > > > > are available in the Git repository at: > > > > https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-9.0-20240219 > > > > for you to fetch changes up to 922e408e12315121d3e09304b8b8f462ea051af1: > > > > target/ppc: optimise ppcemb_tlb_t flushing (2024-02-19 18:09:19 +1000) > > > > ---------------------------------------------------------------- > > * Avocado tests for ppc64 to boot FreeBSD, run guests with emulated > > or nested hypervisor facilities, among other things. > > * Update ppc64 CPU defaults to Power10. > > * Add a new powernv10-rainier machine to better capture differences > > between the different Power10 systems. > > * Implement more device models for powernv. > > * 4xx TLB flushing performance and correctness improvements. > > * Correct gdb implementation to access some important SPRs. > > * Misc cleanups and bug fixes. > > > > I dropped the BHRB patches, they are very close but minor issue only > > noticed recently held them up. Hopefully we can get those and a bunch > > of other outstanding submissions in for 9.0 but this PR was taking too > > long as it was. > > > Peter Maydell (1): > > hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses > > Hi Nick -- this commit went upstream via a different route, and > so it now appears in this pullrequest as a commit with a commit > message but no contents. Could I ask you to respin the pullreq > with that commit dropped, please? Yeah, sorry about that :( I think I noticed it when rebasing but did not check that I'd fixed it. It's nice to keep gunk out of the upstream so I agree, I will respin it. Thanks, Nick
The following changes since commit da96ad4a6a2ef26c83b15fa95e7fceef5147269c: Merge tag 'hw-misc-20240215' of https://github.com/philmd/qemu into staging (2024-02-16 11:05:14 +0000) are available in the Git repository at: https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-9.0-20240219 for you to fetch changes up to 922e408e12315121d3e09304b8b8f462ea051af1: target/ppc: optimise ppcemb_tlb_t flushing (2024-02-19 18:09:19 +1000) ---------------------------------------------------------------- * Avocado tests for ppc64 to boot FreeBSD, run guests with emulated or nested hypervisor facilities, among other things. * Update ppc64 CPU defaults to Power10. * Add a new powernv10-rainier machine to better capture differences between the different Power10 systems. * Implement more device models for powernv. * 4xx TLB flushing performance and correctness improvements. * Correct gdb implementation to access some important SPRs. * Misc cleanups and bug fixes. I dropped the BHRB patches, they are very close but minor issue only noticed recently held them up. Hopefully we can get those and a bunch of other outstanding submissions in for 9.0 but this PR was taking too long as it was. Thanks, Nick ---------------------------------------------------------------- Chalapathi V (3): hw/ppc: Add pnv nest pervasive common chiplet model hw/ppc: Add N1 chiplet model hw/ppc: N1 chiplet wiring Cédric Le Goater (1): spapr: Tag pseries-2.1 - 2.11 machines as deprecated Glenn Miles (9): misc/pca9552: Fix inverted input status misc/pca9552: Let external devices set pca9552 inputs ppc/pnv: New powernv10-rainier machine type ppc/pnv: Add pca9552 to powernv10-rainier for PCIe hotplug power control ppc/pnv: Wire up pca9552 GPIO pins for PCIe hotplug power control ppc/pnv: Use resettable interface to reset child I2C buses misc: Add a pca9554 GPIO device model ppc/pnv: Add a pca9554 I2C device to powernv10-rainier ppc/pnv: Test pnv i2c master and connected devices Harsh Prateek Bora (2): ppc/spapr: Introduce SPAPR_IRQ_NR_IPIS to refer IRQ range for CPU IPIs. ppc/spapr: Initialize max_cpus limit to SPAPR_IRQ_NR_IPIS. Nicholas Piggin (28): target/ppc: Fix lxv/stxv MSR facility check target/ppc: Fix crash on machine check caused by ifetch tests/avocado: mark boot_linux.py long runtime instead of flaky tests/avocado: improve flaky ppc/pnv boot_linux_console.py test tests/avocado: ppc add powernv10 boot_linux_console test tests/avocado: Add ppc pseries and powernv hash MMU tests tests/avocado: Add pseries KVM boot_linux test tests/avocado: ppc add hypervisor tests tests/avocado: Add FreeBSD distro boot tests for ppc tests/avocado: Use default CPU for pseries machine ppc/pnv: Update skiboot to v7.1 target/ppc: Rename registers to match ISA ppc/spapr: change pseries machine default to POWER10 CPU ppc/pnv: Change powernv default to powernv10 target/ppc: Rename TBL to TB on 64-bit target/ppc: Improve timebase register defines naming target/ppc: Fix move-to timebase SPR access permissions ppc/pnv: Add POWER9/10 chiptod model ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines ppc/pnv: Implement the ChipTOD to Core transfer target/ppc: Implement core timebase state machine and TFMR target/ppc: Add SMT support to time facilities target/ppc: Fix 440 tlbwe TLB invalidation gaps target/ppc: Factor out 4xx ppcemb_tlb_t flushing target/ppc: 4xx don't flush TLB for a newly written software TLB entry target/ppc: 4xx optimise tlbwe_lo TLB flushing target/ppc: 440 optimise tlbwe TLB flushing target/ppc: optimise ppcemb_tlb_t flushing Peter Maydell (1): hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses Philippe Mathieu-Daudé (4): hw/ppc/spapr: Add missing license hw/ppc/spapr_hcall: Allow elision of softmmu_resize_hpt_prep hw/ppc/spapr_hcall: Rename {softmmu -> vhyp_mmu}_resize_hpt_pr hw/ppc/spapr: Rename 'softmmu' -> 'vhyp_mmu' Saif Abrar (1): target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U MAINTAINERS | 11 +- docs/about/deprecated.rst | 8 + docs/devel/testing.rst | 11 + hw/misc/Kconfig | 4 + hw/misc/meson.build | 1 + hw/misc/pca9552.c | 58 ++- hw/misc/pca9554.c | 328 +++++++++++++++ hw/ppc/Kconfig | 2 + hw/ppc/meson.build | 5 +- hw/ppc/pnv.c | 131 +++++- hw/ppc/pnv_chiptod.c | 586 +++++++++++++++++++++++++++ hw/ppc/pnv_i2c.c | 146 +------ hw/ppc/pnv_n1_chiplet.c | 173 ++++++++ hw/ppc/pnv_nest_pervasive.c | 208 ++++++++++ hw/ppc/spapr.c | 12 +- hw/ppc/spapr_hcall.c | 12 +- hw/ppc/spapr_irq.c | 6 +- hw/ppc/{spapr_softmmu.c => spapr_vhyp_mmu.c} | 13 +- hw/ppc/trace-events | 4 + include/hw/i2c/pnv_i2c_regs.h | 143 +++++++ include/hw/misc/pca9552.h | 3 +- include/hw/misc/pca9554.h | 36 ++ include/hw/misc/pca9554_regs.h | 19 + include/hw/ppc/pnv.h | 3 + include/hw/ppc/pnv_chip.h | 5 + include/hw/ppc/pnv_chiptod.h | 53 +++ include/hw/ppc/pnv_n1_chiplet.h | 32 ++ include/hw/ppc/pnv_nest_pervasive.h | 32 ++ include/hw/ppc/pnv_xscom.h | 18 + include/hw/ppc/spapr.h | 9 +- include/hw/ppc/spapr_irq.h | 14 +- pc-bios/skiboot.lid | Bin 2527240 -> 2527328 bytes target/ppc/cpu.h | 57 ++- target/ppc/cpu_init.c | 20 +- target/ppc/excp_helper.c | 36 +- target/ppc/gdbstub.c | 40 +- target/ppc/helper_regs.c | 41 +- target/ppc/mmu_helper.c | 105 +++-- target/ppc/ppc-qmp-cmds.c | 4 + target/ppc/tcg-stub.c | 15 - target/ppc/timebase_helper.c | 309 +++++++++++++- target/ppc/translate.c | 42 +- target/ppc/translate/vsx-impl.c.inc | 2 +- tests/avocado/boot_freebsd.py | 174 ++++++++ tests/avocado/boot_linux.py | 16 +- tests/avocado/boot_linux_console.py | 11 +- tests/avocado/migration.py | 1 - tests/avocado/ppc_hv_tests.py | 203 ++++++++++ tests/avocado/ppc_powernv.py | 23 +- tests/avocado/ppc_pseries.py | 20 +- tests/qtest/meson.build | 1 + tests/qtest/pca9552-test.c | 6 +- tests/qtest/pnv-host-i2c-test.c | 491 ++++++++++++++++++++++ tests/qtest/pnv-xscom-test.c | 61 +-- tests/qtest/pnv-xscom.h | 80 ++++ 55 files changed, 3492 insertions(+), 352 deletions(-) create mode 100644 hw/misc/pca9554.c create mode 100644 hw/ppc/pnv_chiptod.c create mode 100644 hw/ppc/pnv_n1_chiplet.c create mode 100644 hw/ppc/pnv_nest_pervasive.c rename hw/ppc/{spapr_softmmu.c => spapr_vhyp_mmu.c} (97%) create mode 100644 include/hw/i2c/pnv_i2c_regs.h create mode 100644 include/hw/misc/pca9554.h create mode 100644 include/hw/misc/pca9554_regs.h create mode 100644 include/hw/ppc/pnv_chiptod.h create mode 100644 include/hw/ppc/pnv_n1_chiplet.h create mode 100644 include/hw/ppc/pnv_nest_pervasive.h create mode 100644 tests/avocado/boot_freebsd.py create mode 100644 tests/avocado/ppc_hv_tests.py create mode 100644 tests/qtest/pnv-host-i2c-test.c create mode 100644 tests/qtest/pnv-xscom.h