Message ID | 20240215173538.2430599-1-peter.maydell@linaro.org |
---|---|
State | New |
Headers | show |
On Thu, 15 Feb 2024 at 17:35, Peter Maydell <peter.maydell@linaro.org> wrote: > > The following changes since commit 5767815218efd3cbfd409505ed824d5f356044ae: > > Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2024-02-14 15:45:52 +0000) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240215 > > for you to fetch changes up to f780e63fe731b058fe52d43653600d8729a1b5f2: > > docs: Add documentation for the mps3-an536 board (2024-02-15 14:32:39 +0000) > > ---------------------------------------------------------------- > target-arm queue: > * hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC > * linux-user/aarch64: Choose SYNC as the preferred MTE mode > * Fix some errors in SVE/SME handling of MTE tags > * hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses > * hw/block/tc58128: Don't emit deprecation warning under qtest > * tests/qtest: Fix handling of npcm7xx and GMAC tests > * hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ > * tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend > * Don't assert on vmload/vmsave of M-profile CPUs > * hw/arm/smmuv3: add support for stage 1 access fault > * hw/arm/stellaris: QOM cleanups > * Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs > * Improve Cortex_R52 IMPDEF sysreg modelling > * Allow access to SPSR_hyp from hyp mode > * New board model mps3-an536 (Cortex-R52) > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0 for any user-visible changes. -- PMM