diff mbox series

[v2,3/7] target/riscv: Change gen_goto_tb to work on displacements

Message ID 20230523135939.299246-4-liweiwei@iscas.ac.cn
State New
Headers show
Series target/riscv: Add support for PC-relative translation | expand

Commit Message

Weiwei Li May 23, 2023, 1:59 p.m. UTC 
Reduce reliance on absolute value to prepare for PC-relative translation.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
 target/riscv/translate.c                | 8 +++++---
 2 files changed, 7 insertions(+), 5 deletions(-)

Comments

Richard Henderson May 23, 2023, 8:29 p.m. UTC | #1 
On 5/23/23 06:59, Weiwei Li wrote:
> Reduce reliance on absolute value to prepare for PC-relative translation.
> 
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
>   target/riscv/translate.c                | 8 +++++---
>   2 files changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/tar

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
Alistair Francis May 26, 2023, 2:04 a.m. UTC | #2 
On Wed, May 24, 2023 at 12:14 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Reduce reliance on absolute value to prepare for PC-relative translation.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
>  target/riscv/translate.c                | 8 +++++---
>  2 files changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index 0d52a80178..81ed0d200a 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -171,7 +171,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
>      } else {
>          tcg_gen_brcond_tl(cond, src1, src2, l);
>      }
> -    gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
> +    gen_goto_tb(ctx, 1, ctx->cur_insn_len);
>
>      gen_set_label(l); /* branch taken */
>
> @@ -182,7 +182,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
>          gen_pc_plus_diff(target_pc, ctx, next_pc);
>          gen_exception_inst_addr_mis(ctx, target_pc);
>      } else {
> -        gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
> +        gen_goto_tb(ctx, 0, a->imm);
>      }
>      ctx->base.is_jmp = DISAS_NORETURN;
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index d756866925..8a371c0d75 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -281,8 +281,10 @@ static void exit_tb(DisasContext *ctx)
>      tcg_gen_exit_tb(NULL, 0);
>  }
>
> -static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
> +static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
>  {
> +    target_ulong dest = ctx->base.pc_next + diff;
> +
>       /*
>        * Under itrigger, instruction executes one by one like singlestep,
>        * direct block chain benefits will be small.
> @@ -557,7 +559,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
>      }
>
>      gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
> -    gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
> +    gen_goto_tb(ctx, 0, imm); /* must use this for safety */
>      ctx->base.is_jmp = DISAS_NORETURN;
>  }
>
> @@ -1228,7 +1230,7 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
>
>      switch (ctx->base.is_jmp) {
>      case DISAS_TOO_MANY:
> -        gen_goto_tb(ctx, 0, ctx->base.pc_next);
> +        gen_goto_tb(ctx, 0, 0);
>          break;
>      case DISAS_NORETURN:
>          break;
> --
> 2.25.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 0d52a80178..81ed0d200a 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -171,7 +171,7 @@  static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
     } else {
         tcg_gen_brcond_tl(cond, src1, src2, l);
     }
-    gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
+    gen_goto_tb(ctx, 1, ctx->cur_insn_len);
 
     gen_set_label(l); /* branch taken */
 
@@ -182,7 +182,7 @@  static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
         gen_pc_plus_diff(target_pc, ctx, next_pc);
         gen_exception_inst_addr_mis(ctx, target_pc);
     } else {
-        gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
+        gen_goto_tb(ctx, 0, a->imm);
     }
     ctx->base.is_jmp = DISAS_NORETURN;
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d756866925..8a371c0d75 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -281,8 +281,10 @@  static void exit_tb(DisasContext *ctx)
     tcg_gen_exit_tb(NULL, 0);
 }
 
-static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
 {
+    target_ulong dest = ctx->base.pc_next + diff;
+
      /*
       * Under itrigger, instruction executes one by one like singlestep,
       * direct block chain benefits will be small.
@@ -557,7 +559,7 @@  static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
     }
 
     gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
-    gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
+    gen_goto_tb(ctx, 0, imm); /* must use this for safety */
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
@@ -1228,7 +1230,7 @@  static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
 
     switch (ctx->base.is_jmp) {
     case DISAS_TOO_MANY:
-        gen_goto_tb(ctx, 0, ctx->base.pc_next);
+        gen_goto_tb(ctx, 0, 0);
         break;
     case DISAS_NORETURN:
         break;