diff mbox series

[9/9] hw/ssi: npcm7xx_fiu: Correct the dummy cycle emulation logic

Message ID 20210114150902.11515-10-bmeng.cn@gmail.com
State New
Headers show
Series hw/block: m25p80: Fix the mess of dummy bytes needed for fast read commands | expand

Commit Message

Bin Meng Jan. 14, 2021, 3:09 p.m. UTC 
From: Bin Meng <bin.meng@windriver.com>

I believe send_dummy_bits() should also be fixed, but I really don't
know how based on my pure read/guess of the codes since there is no
public datasheet available for this NPCM7xx SoC.

Signed-off-by: Bin Meng <bin.meng@windriver.com>

---

 hw/ssi/npcm7xx_fiu.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)
diff mbox series

Patch

diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
index 5040132b07..e76fb5ad9f 100644
--- a/hw/ssi/npcm7xx_fiu.c
+++ b/hw/ssi/npcm7xx_fiu.c
@@ -150,7 +150,7 @@  static uint64_t npcm7xx_fiu_flash_read(void *opaque, hwaddr addr,
     NPCM7xxFIUState *fiu = f->fiu;
     uint64_t value = 0;
     uint32_t drd_cfg;
-    int dummy_cycles;
+    int dummy_bytes;
     int i;
 
     if (fiu->active_cs != -1) {
@@ -180,10 +180,8 @@  static uint64_t npcm7xx_fiu_flash_read(void *opaque, hwaddr addr,
         break;
     }
 
-    /* Flash chip model expects one transfer per dummy bit, not byte */
-    dummy_cycles =
-        (FIU_DRD_CFG_DBW(drd_cfg) * 8) >> FIU_DRD_CFG_ACCTYPE(drd_cfg);
-    for (i = 0; i < dummy_cycles; i++) {
+    dummy_bytes = FIU_DRD_CFG_DBW(drd_cfg) >> FIU_DRD_CFG_ACCTYPE(drd_cfg);
+    for (i = 0; i < dummy_bytes; i++) {
         ssi_transfer(fiu->spi, 0);
     }