diff mbox series

[10/10] target/arm: Fix writing to FPSCR.FZ16 on M-profile

Message ID 20201012153746.9996-11-peter.maydell@linaro.org
State New
Headers show
Series target/arm: Various v8.1M minor features | expand

Commit Message

Peter Maydell Oct. 12, 2020, 3:37 p.m. UTC 
The M-profile specific part of the sanitizing of the value to
be written to the FPSCR used a mask which always zeroed bit 19,
which is FZ16. This is incorrect when the CPU supports 16-bit
floating point arithmetic, because the bit should be writeable.

Code earlier in the function already handles making this bit be RES0
if the CPU doesn't implement the FP16 feature, so we can simply stop
masking it out for M-profile.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/vfp_helper.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 350150adbf1..4b0bb2bacfb 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -198,13 +198,14 @@  void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
 
     if (arm_feature(env, ARM_FEATURE_M)) {
         /*
-         * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
+         * M profile FPSCR is RES0 for the QC, STRIDE, LEN bits
          * and also for the trapped-exception-handling bits IxE.
          * From v8.1M with the low-overhead-loop extension bits
          * [18:16] are used for LTPSIZE and (since we don't implement
          * MVE) always read as 4 and ignore writes.
+         * FZ16 has already been handled as RES0 above if needed.
          */
-        val &= 0xf7c0009f;
+        val &= 0xf7c8009f;
         if (cpu_isar_feature(aa32_lob, cpu)) {
             val |= 4 << 16;
         }