Message ID | 20190319124803.13826-17-palmer@sifive.com |
---|---|
State | New |
Headers | show
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[2001:b011:7001:1cad:363a:ebbe:dac8:3f4c]) by smtp.gmail.com with ESMTPSA id s4sm22305577pfe.16.2019.03.19.05.54.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Mar 2019 05:54:58 -0700 (PDT) Date: Tue, 19 Mar 2019 05:48:00 -0700 Message-Id: <20190319124803.13826-17-palmer@sifive.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190319124803.13826-1-palmer@sifive.com> References: <20190319124803.13826-1-palmer@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::530 Subject: [Qemu-devel] [PULL 16/19] riscv: sifive_u: Allow up to 4 CPUs to be created X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> |
Series |
[PULL,01/19] RISC-V: Add 32-bit gdb xml files.
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diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7bc25820feaa..3199238ba01e 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -398,7 +398,10 @@ static void riscv_sifive_u_machine_init(MachineClass *mc) { mc->desc = "RISC-V Board compatible with SiFive U SDK"; mc->init = riscv_sifive_u_init; - mc->max_cpus = 1; + /* The real hardware has 5 CPUs, but one of them is a small embedded power + * management CPU. + */ + mc->max_cpus = 4; } DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)