[PULL,00/10] target-mips queue

Hi,

This pull request contains various fixes, improvements and clean-ups.

Thanks,
Leon

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>

The following changes since commit 16a1b6e97c2a2919fd296db4bea2f9da2ad3cc4d:

  target-cris: update CPU state save/load to use VMStateDescription (2015-09-17 14:31:38 +0100)

are available in the git repository at:

  git://github.com/lalrae/qemu.git tags/mips-20150918

for you to fetch changes up to 9c708c7f9fbb813a3fac02f2728e51e62f2f5ffc:

  target-mips: improve exception handling (2015-09-18 12:07:24 +0100)

----------------------------------------------------------------
MIPS patches 2015-09-18

Changes:
* fixes for rdhwr, tlbwr, mtc0, recip.fmt, rsqrt.fmt and daui instructions
* removal of MIPS_DEBUG code
* use tcg_gen_extrh_i64_i32()
* improve random tlb index generation in cpu_mips_get_random()
* exception handling improvements to correctly restore icount

----------------------------------------------------------------
Alex Smith (1):
      target-mips: Fix RDHWR on CP0.Count

Aurelien Jarno (2):
      target-mips: get rid of MIPS_DEBUG
      target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS

Leon Alrae (3):
      target-mips: fix corner case in TLBWR causing QEMU to hang
      target-mips: add missing restriction in DAUI instruction
      target-mips: correct MTC0 instruction on MIPS64

Pavel Dovgaluk (1):
      target-mips: improve exception handling

Petar Jovanovic (1):
      target-mips: remove wrong checks for recip.fmt and rsqrt.fmt

Richard Henderson (1):
      target-mips: Use tcg_gen_extrh_i64_i32

Serge Vakulenko (1):
      pic32: use LCG algorithm for generated random index of TLBWR instruction

 hw/mips/cputimer.c       |   14 +-
 target-mips/cpu.h        |   24 +
 target-mips/helper.h     |    1 +
 target-mips/msa_helper.c |  158 ++++---
 target-mips/op_helper.c  |  263 ++++++-----
 target-mips/translate.c  | 1104 ++++++++++------------------------------------
 6 files changed, 496 insertions(+), 1068 deletions(-)

On 18 September 2015 at 12:25, Leon Alrae <leon.alrae@imgtec.com> wrote:
> Hi,
>
> This pull request contains various fixes, improvements and clean-ups.
>
> Thanks,
> Leon
>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
>
> The following changes since commit 16a1b6e97c2a2919fd296db4bea2f9da2ad3cc4d:
>
>   target-cris: update CPU state save/load to use VMStateDescription (2015-09-17 14:31:38 +0100)
>
> are available in the git repository at:
>
>   git://github.com/lalrae/qemu.git tags/mips-20150918
>
> for you to fetch changes up to 9c708c7f9fbb813a3fac02f2728e51e62f2f5ffc:
>
>   target-mips: improve exception handling (2015-09-18 12:07:24 +0100)
>
> ----------------------------------------------------------------
> MIPS patches 2015-09-18
>
> Changes:
> * fixes for rdhwr, tlbwr, mtc0, recip.fmt, rsqrt.fmt and daui instructions
> * removal of MIPS_DEBUG code
> * use tcg_gen_extrh_i64_i32()
> * improve random tlb index generation in cpu_mips_get_random()
> * exception handling improvements to correctly restore icount
>
> ----------------------------------------------------------------

Applied, thanks.

-- PMM