diff mbox

[5/9] target-ppc: Introduce TEXASRU Bit Fields

Message ID 1418920477-11669-6-git-send-email-tommusta@gmail.com
State New
Headers show

Commit Message

Tom Musta Dec. 18, 2014, 4:34 p.m. UTC 
Define mnemonics for the various bit fields in the Transaction
EXception And Summary Register (TEXASR).
---
 target-ppc/cpu.h |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

Comments

Alexander Graf Dec. 18, 2014, 5:02 p.m. UTC | #1 
On 18.12.14 17:34, Tom Musta wrote:
> Define mnemonics for the various bit fields in the Transaction
> EXception And Summary Register (TEXASR).

This is missing an SoB line.


Alex
Tom Musta Dec. 18, 2014, 6:10 p.m. UTC | #2 
On 12/18/2014 11:02 AM, Alexander Graf wrote:
> 
> 
> On 18.12.14 17:34, Tom Musta wrote:
>> Define mnemonics for the various bit fields in the Transaction
>> EXception And Summary Register (TEXASR).
> 
> This is missing an SoB line.
> 
> 
> Alex
> 

Sorry about that.  I will publish a V2 but may wait a day or so for any other other comments.
Alexander Graf Dec. 18, 2014, 6:29 p.m. UTC | #3 
On 18.12.14 19:10, Tom Musta wrote:
> On 12/18/2014 11:02 AM, Alexander Graf wrote:
>>
>>
>> On 18.12.14 17:34, Tom Musta wrote:
>>> Define mnemonics for the various bit fields in the Transaction
>>> EXception And Summary Register (TEXASR).
>>
>> This is missing an SoB line.
>>
>>
>> Alex
>>
> 
> Sorry about that.  I will publish a V2 but may wait a day or so for any other other comments.

The patches look good IMHO, just reply with your SoB line and I'll apply
the rest too :)


Alex
Tom Musta Dec. 18, 2014, 6:41 p.m. UTC | #4 
On 12/18/2014 12:29 PM, Alexander Graf wrote:
> 
> 
> On 18.12.14 19:10, Tom Musta wrote:
>> On 12/18/2014 11:02 AM, Alexander Graf wrote:
>>>
>>>
>>> On 18.12.14 17:34, Tom Musta wrote:
>>>> Define mnemonics for the various bit fields in the Transaction
>>>> EXception And Summary Register (TEXASR).
>>>
>>> This is missing an SoB line.
>>>
>>>
>>> Alex
>>>
>>
>> Sorry about that.  I will publish a V2 but may wait a day or so for any other other comments.
> 
> The patches look good IMHO, just reply with your SoB line and I'll apply
> the rest too :)
> 
> 
> Alex
> 

Signed-off-by: Tom Musta <tommusta@gmail.com>
diff mbox

Patch

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 38176c0..91a03f6 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -558,6 +558,26 @@  struct ppc_slb_t {
 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation                          */
 #define ESR_MIF   (1 << (63 - 62)) /* Misaligned instruction (VLE)           */
 
+/* Transaction EXception And Summary Register bits                           */
+#define TEXASR_FAILURE_PERSISTENT                (63 - 7)
+#define TEXASR_DISALLOWED                        (63 - 8)
+#define TEXASR_NESTING_OVERFLOW                  (63 - 9)
+#define TEXASR_FOOTPRINT_OVERFLOW                (63 - 10)
+#define TEXASR_SELF_INDUCED_CONFLICT             (63 - 11)
+#define TEXASR_NON_TRANSACTIONAL_CONFLICT        (63 - 12)
+#define TEXASR_TRANSACTION_CONFLICT              (63 - 13)
+#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
+#define TEXASR_IMPLEMENTATION_SPECIFIC           (63 - 15)
+#define TEXASR_INSTRUCTION_FETCH_CONFLICT        (63 - 16)
+#define TEXASR_ABORT                             (63 - 31)
+#define TEXASR_SUSPENDED                         (63 - 32)
+#define TEXASR_PRIVILEGE_HV                      (63 - 34)
+#define TEXASR_PRIVILEGE_PR                      (63 - 35)
+#define TEXASR_FAILURE_SUMMARY                   (63 - 36)
+#define TEXASR_TFIAR_EXACT                       (63 - 37)
+#define TEXASR_ROT                               (63 - 38)
+#define TEXASR_TRANSACTION_LEVEL                 (63 - 52) /* 12 bits */
+
 enum {
     POWERPC_FLAG_NONE     = 0x00000000,
     /* Flag for MSR bit 25 signification (VRE/SPE)                           */