From patchwork Thu Dec 18 16:34:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Musta X-Patchwork-Id: 422616 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 525BD1400B7 for ; Fri, 19 Dec 2014 03:44:36 +1100 (AEDT) Received: from localhost ([::1]:54780 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y1eBm-00057l-If for incoming@patchwork.ozlabs.org; Thu, 18 Dec 2014 11:44:34 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34605) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y1e41-0000dT-98 for qemu-devel@nongnu.org; Thu, 18 Dec 2014 11:36:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y1e3r-0006fx-Ob for qemu-devel@nongnu.org; Thu, 18 Dec 2014 11:36:33 -0500 Received: from mail-ie0-x22c.google.com ([2607:f8b0:4001:c03::22c]:50486) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y1e3r-0006fl-KW; Thu, 18 Dec 2014 11:36:23 -0500 Received: by mail-ie0-f172.google.com with SMTP id tr6so1429556ieb.31; Thu, 18 Dec 2014 08:36:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W6CV3xWzJDSEQX6RbfXSdpOD2to9sjjM38EEF8zVeKY=; b=migx60LHHz8wZ6SJWyLpzcwtcpn+3dqEOKHIfMzYOVySUgcjlqPCVlPA2mDmD8fyyi +4x5poWFF+FGFEVz1m4AJCAk2H2oheq/0DYRKT4DV0RXuu2+0FnKzPn1EijYofLaRfoA txb5LmU6qyqbRJj7BiDxLIdscH5pgDOQhHtC3ivPLT+J8wSlfWVfIGSmNSNucJXHWm+4 9u0i0uxuIJcuvB4ZtVByap89dfMzQUPHxelGwiK3+AGS+medqulOuuzQlyFRRreYqFoQ 2n8G9nloByzP7rzggM6xF/GLwjTCsocF4XdsibHv297WNiBPZfMf7LU6nOPmi252n0Km BqLQ== X-Received: by 10.42.71.194 with SMTP id l2mr2621296icj.71.1418920583219; Thu, 18 Dec 2014 08:36:23 -0800 (PST) Received: from tmusta-sc.rchland.ibm.com (rchp4.rochester.ibm.com. [129.42.161.36]) by mx.google.com with ESMTPSA id n4sm9436024igr.15.2014.12.18.08.36.22 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 18 Dec 2014 08:36:22 -0800 (PST) From: Tom Musta To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Date: Thu, 18 Dec 2014 10:34:33 -0600 Message-Id: <1418920477-11669-6-git-send-email-tommusta@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1418920477-11669-1-git-send-email-tommusta@gmail.com> References: <1418920477-11669-1-git-send-email-tommusta@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4001:c03::22c Cc: Tom Musta , agraf@suse.de Subject: [Qemu-devel] [PATCH 5/9] target-ppc: Introduce TEXASRU Bit Fields X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Define mnemonics for the various bit fields in the Transaction EXception And Summary Register (TEXASR). Signed-off-by: Tom Musta --- target-ppc/cpu.h | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 38176c0..91a03f6 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -558,6 +558,26 @@ struct ppc_slb_t { #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */ #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */ +/* Transaction EXception And Summary Register bits */ +#define TEXASR_FAILURE_PERSISTENT (63 - 7) +#define TEXASR_DISALLOWED (63 - 8) +#define TEXASR_NESTING_OVERFLOW (63 - 9) +#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10) +#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11) +#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12) +#define TEXASR_TRANSACTION_CONFLICT (63 - 13) +#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14) +#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15) +#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16) +#define TEXASR_ABORT (63 - 31) +#define TEXASR_SUSPENDED (63 - 32) +#define TEXASR_PRIVILEGE_HV (63 - 34) +#define TEXASR_PRIVILEGE_PR (63 - 35) +#define TEXASR_FAILURE_SUMMARY (63 - 36) +#define TEXASR_TFIAR_EXACT (63 - 37) +#define TEXASR_ROT (63 - 38) +#define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */ + enum { POWERPC_FLAG_NONE = 0x00000000, /* Flag for MSR bit 25 signification (VRE/SPE) */