| Message ID | 1253313049-25874-3-git-send-email-andre.przywara@amd.com |
|---|---|
| State | Superseded |
| Headers | show |
On Sat, Sep 19, 2009 at 12:30:47AM +0200, Andre Przywara wrote: > AMD CPUs featuring a shortcut to access CR8 even from 32-bit mode. > If you use the LOCK prefix with "mov CR0", it accesses CR8 instead. > This behavior is guarded by the CR8_LEGACY CPUID bit > (Fn8000_0001:ECX[1]). Thanks, applied. > Signed-off-by: Andre Przywara <andre.przywara@amd.com> > --- > target-i386/translate.c | 4 ++++ > 1 files changed, 4 insertions(+), 0 deletions(-) > > diff --git a/target-i386/translate.c b/target-i386/translate.c > index aaa4492..134c870 100644 > --- a/target-i386/translate.c > +++ b/target-i386/translate.c > @@ -7362,6 +7362,10 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) > ot = OT_QUAD; > else > ot = OT_LONG; > + if ((prefixes & PREFIX_LOCK) && (reg == 0) && > + (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) { > + reg = 8; > + } > switch(reg) { > case 0: > case 2: > -- > 1.6.1.3 > > > > >
diff --git a/target-i386/translate.c b/target-i386/translate.c index aaa4492..134c870 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7362,6 +7362,10 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) ot = OT_QUAD; else ot = OT_LONG; + if ((prefixes & PREFIX_LOCK) && (reg == 0) && + (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) { + reg = 8; + } switch(reg) { case 0: case 2:
AMD CPUs featuring a shortcut to access CR8 even from 32-bit mode. If you use the LOCK prefix with "mov CR0", it accesses CR8 instead. This behavior is guarded by the CR8_LEGACY CPUID bit (Fn8000_0001:ECX[1]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> --- target-i386/translate.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)