Show patches with: Submitter = Frank Chang       |    State = Action Required       |    Archived = No       |   1060 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V Add RISC-V RVV Zve32f and Zve64f extensions - - 1 - --- 2021-12-29 Frank Chang New
[02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns Add RISC-V RVV Zve32f and Zve64f extensions - - 1 - --- 2021-12-29 Frank Chang New
[03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns Add RISC-V RVV Zve32f and Zve64f extensions - - - - --- 2021-12-29 Frank Chang New
[04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns Add RISC-V RVV Zve32f and Zve64f extensions - - 1 - --- 2021-12-29 Frank Chang New
[05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns Add RISC-V RVV Zve32f and Zve64f extensions - - 1 - --- 2021-12-29 Frank Chang New
[06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns Add RISC-V RVV Zve32f and Zve64f extensions - - 1 - --- 2021-12-29 Frank Chang New
[07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns Add RISC-V RVV Zve32f and Zve64f extensions - - 1 - --- 2021-12-29 Frank Chang New
[08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns Add RISC-V RVV Zve32f and Zve64f extensions - - 1 - --- 2021-12-29 Frank Chang New
[09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns Add RISC-V RVV Zve32f and Zve64f extensions - - 1 - --- 2021-12-29 Frank Chang New
[1/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check funtion for widening fp insns Fix RVV calling incorrect RFV/RVD check functions bug - - - - --- 2021-12-29 Frank Chang New
[1/4] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set hw/dma: Align SiFive PDMA behavior with real hardware - - 1 2 --- 2021-09-10 Frank Chang New
[1/9] target/riscv: debug: Determine the trigger type from tdata1.type Improve RISC-V Debug support - - 1 - --- 2022-06-10 Frank Chang New
[10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on Add RISC-V RVV Zve32f and Zve64f extensions - - 1 - --- 2021-12-29 Frank Chang New
[11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V Add RISC-V RVV Zve32f and Zve64f extensions - - 1 - --- 2021-12-29 Frank Chang New
[12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns Add RISC-V RVV Zve32f and Zve64f extensions - - 1 - --- 2021-12-29 Frank Chang New
[13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns Add RISC-V RVV Zve32f and Zve64f extensions - - 1 - --- 2021-12-29 Frank Chang New
[14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns Add RISC-V RVV Zve32f and Zve64f extensions - - 1 - --- 2021-12-29 Frank Chang New
[15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns Add RISC-V RVV Zve32f and Zve64f extensions - - 1 - --- 2021-12-29 Frank Chang New
[16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns Add RISC-V RVV Zve32f and Zve64f extensions - - 1 - --- 2021-12-29 Frank Chang New
[17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on Add RISC-V RVV Zve32f and Zve64f extensions - - 1 - --- 2021-12-29 Frank Chang New
[18/76] target/riscv: rvv-1.0: configure instructions support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[19/76] target/riscv: rvv-1.0: stride load and store instructions support vector extension v1.0 - - 1 - --- 2021-10-15 Frank Chang New
[2/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check funtion for widening fp/int type-conver… Fix RVV calling incorrect RFV/RVD check functions bug - - - - --- 2021-12-29 Frank Chang New
[2/4] hw/dma: sifive_pdma: claim bit must be set before DMA transactions hw/dma: Align SiFive PDMA behavior with real hardware - - 1 2 --- 2021-09-10 Frank Chang New
[2/9] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content Improve RISC-V Debug support - - 1 - --- 2022-06-10 Frank Chang New
[20/76] target/riscv: rvv-1.0: index load and store instructions Untitled series #267190 - - 1 - --- 2021-10-15 Frank Chang New
[21/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns support vector extension v1.0 - - 2 - --- 2021-10-15 Frank Chang New
[22/76] target/riscv: rvv-1.0: fault-only-first unit stride load Untitled series #267192 - - 2 - --- 2021-10-15 Frank Chang New
[23/76] target/riscv: rvv-1.0: amo operations support vector extension v1.0 - - 1 - --- 2021-10-15 Frank Chang New
[29/76] target/riscv: rvv-1.0: mask population count instruction support vector extension v1.0 - - 1 - --- 2021-10-15 Frank Chang New
[3/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check funtion for narrowing fp/int type-conve… Fix RVV calling incorrect RFV/RVD check functions bug - - - - --- 2021-12-29 Frank Chang New
[3/4] hw/dma: sifive_pdma: allow non-multiple transaction size transactions hw/dma: Align SiFive PDMA behavior with real hardware - - 2 2 --- 2021-09-10 Frank Chang New
[3/9] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs Improve RISC-V Debug support - - - - --- 2022-06-10 Frank Chang New
[4/4] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer hw/dma: Align SiFive PDMA behavior with real hardware - - 1 2 --- 2021-09-10 Frank Chang New
[4/9] target/riscv: debug: Restrict the range of tselect value can be written Improve RISC-V Debug support - - 1 - --- 2022-06-10 Frank Chang New
[5/9] target/riscv: debug: Introduce tinfo CSR Improve RISC-V Debug support - - 1 - --- 2022-06-10 Frank Chang New
[6/9] target/riscv: debug: Create common trigger actions function Improve RISC-V Debug support - - - - --- 2022-06-10 Frank Chang New
[7/9] target/riscv: debug: Check VU/VS modes for type 2 trigger Improve RISC-V Debug support - - 1 - --- 2022-06-10 Frank Chang New
[8/9] target/riscv: debug: Return 0 if previous value written to tselect >= number of triggers Improve RISC-V Debug support - - - - --- 2022-06-10 Frank Chang New
[9/9] target/riscv: debug: Add initial support of type 6 trigger Improve RISC-V Debug support - - 1 - --- 2022-06-10 Frank Chang New
[RESEND,v2,1/4] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set hw/dma: Align SiFive PDMA behavior with real hardware - - 1 2 --- 2021-09-12 Frank Chang New
[RESEND,v2,2/4] hw/dma: sifive_pdma: claim bit must be set before DMA transactions hw/dma: Align SiFive PDMA behavior with real hardware - - 1 2 --- 2021-09-12 Frank Chang New
[RESEND,v2,3/4] hw/dma: sifive_pdma: allow non-multiple transaction size transactions hw/dma: Align SiFive PDMA behavior with real hardware - - 2 2 --- 2021-09-12 Frank Chang New
[RESEND,v2,4/4] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer hw/dma: Align SiFive PDMA behavior with real hardware - - 1 2 --- 2021-09-12 Frank Chang New
[RESEND,v2] target/riscv: Fix typo of mimpid cpu option [RESEND,v2] target/riscv: Fix typo of mimpid cpu option - 1 1 - --- 2022-05-23 Frank Chang New
[RESEND,v2] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty() [RESEND,v2] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty() - - 2 1 --- 2021-09-17 Frank Chang New
[RFC,01/15] target/riscv: reformat @sh format encoding for B-extension support subsets of bitmanip extension - - - - --- 2020-11-18 Frank Chang New
[RFC,01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion target/riscv: support vector extension v0.9 - - 1 - --- 2020-07-10 Frank Chang New
[RFC,02/15] target/riscv: rvb: count leading/trailing zeros support subsets of bitmanip extension - - - - --- 2020-11-18 Frank Chang New
[RFC,02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() target/riscv: support vector extension v0.9 - - 1 - --- 2020-07-10 Frank Chang New
[RFC,03/15] target/riscv: rvb: count bits set support subsets of bitmanip extension - - 1 - --- 2020-11-18 Frank Chang New
[RFC,03/65] target/riscv: fix return value of do_opivx_widen() target/riscv: support vector extension v0.9 - - 1 - --- 2020-07-10 Frank Chang New
[RFC,04/15] target/riscv: rvb: logic-with-negate support subsets of bitmanip extension - - - - --- 2020-11-18 Frank Chang New
[RFC,04/65] target/riscv: fix vill bit index in vtype register target/riscv: support vector extension v0.9 - - 1 - --- 2020-07-10 Frank Chang New
[RFC,05/15] target/riscv: rvb: pack two words into one register support subsets of bitmanip extension - - - - --- 2020-11-18 Frank Chang New
[RFC,05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,06/15] target/riscv: rvb: min/max instructions support subsets of bitmanip extension - - 1 - --- 2020-11-18 Frank Chang New
[RFC,06/65] target/riscv: rvv-0.9: add vcsr register target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,07/15] target/riscv: rvb: sign-extend instructions support subsets of bitmanip extension - - 1 - --- 2020-11-18 Frank Chang New
[RFC,07/65] target/riscv: rvv-0.9: add vector context status target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,08/15] target/riscv: rvb: single-bit instructions support subsets of bitmanip extension - - - - --- 2020-11-18 Frank Chang New
[RFC,08/65] target/riscv: rvv-0.9: update mstatus_vs by tb_flags target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,09/15] target/riscv: rvb: shift ones support subsets of bitmanip extension - - - - --- 2020-11-18 Frank Chang New
[RFC,09/65] target/riscv: rvv-0.9: add vlenb register target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,1/1] target/riscv: add support of RNMI target/riscv: add RNMI support - - - - --- 2021-03-09 Frank Chang New
[RFC,10/15] target/riscv: rvb: rotate (left/right) support subsets of bitmanip extension - - - - --- 2020-11-18 Frank Chang New
[RFC,10/65] target/riscv: rvv-0.9: remove MLEN calculations target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,11/15] target/riscv: rvb: generalized reverse support subsets of bitmanip extension - - - - --- 2020-11-18 Frank Chang New
[RFC,11/65] target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,12/15] target/riscv: rvb: generalized or-combine support subsets of bitmanip extension - - - - --- 2020-11-18 Frank Chang New
[RFC,12/65] target/riscv: rvv-0.9: update check functions target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,13/15] target/riscv: rvb: address calculation support subsets of bitmanip extension - - 1 - --- 2020-11-18 Frank Chang New
[RFC,13/65] target/riscv: rvv-0.9: configure instructions target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,14/15] target/riscv: rvb: add/sub with postfix zero-extend support subsets of bitmanip extension - - - - --- 2020-11-18 Frank Chang New
[RFC,14/65] target/riscv: rvv-0.9: stride load and store instructions target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,15/15] target/riscv: rvb: support and turn on B-extension from command line support subsets of bitmanip extension - - 1 - --- 2020-11-18 Frank Chang New
[RFC,15/65] target/riscv: rvv-0.9: index load and store instructions target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,16/65] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,17/65] target/riscv: rvv-0.9: fault-only-first unit stride load target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,18/65] target/riscv: rvv-0.9: amo operations target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,19/65] target/riscv: rvv-0.9: load/store whole register instructions target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,21/65] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,22/65] target/riscv: rvv-0.9: floating-point square-root instruction target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,23/65] target/riscv: rvv-0.9: floating-point classify instructions target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,24/65] target/riscv: rvv-0.9: mask population count instruction target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,25/65] target/riscv: rvv-0.9: find-first-set mask bit instruction target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,26/65] target/riscv: rvv-0.9: set-X-first mask bit instructions target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,27/65] target/riscv: rvv-0.9: iota instruction target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,28/65] target/riscv: rvv-0.9: element index instruction target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,29/65] target/riscv: rvv-0.9: integer scalar move instructions target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,30/65] target/riscv: rvv-0.9: floating-point scalar move instructions target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,31/65] target/riscv: rvv-0.9: whole register move instructions target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,32/65] target/riscv: rvv-0.9: integer extension instructions target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,33/65] target/riscv: rvv-0.9: single-width averaging add and subtract instructions target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,34/65] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,35/65] target/riscv: rvv-0.9: narrowing integer right shift instructions target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,36/65] target/riscv: rvv-0.9: widening integer multiply-add instructions target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,37/65] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
[RFC,38/65] target/riscv: rvv-0.9: integer merge and move instructions target/riscv: support vector extension v0.9 - - - - --- 2020-07-10 Frank Chang New
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