diff mbox series

[08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns

Message ID 20211229023348.12606-9-frank.chang@sifive.com
State New
Headers show
Series Add RISC-V RVV Zve32f and Zve64f extensions | expand

Commit Message

Frank Chang Dec. 29, 2021, 2:33 a.m. UTC 
From: Frank Chang <frank.chang@sifive.com>

Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 32 +++++++++++++++++++------
 1 file changed, 25 insertions(+), 7 deletions(-)

Comments

Alistair Francis Jan. 17, 2022, 10:51 p.m. UTC | #1 
On Wed, Dec 29, 2021 at 12:42 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Vector widening conversion instructions are provided to and from all
> supported integer EEWs for Zve64f extension.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 32 +++++++++++++++++++------
>  1 file changed, 25 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index d7e288b87f..9ca8d502b2 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -77,6 +77,17 @@ static bool require_zve64f(DisasContext *s)
>      return s->ext_zve64f ? s->sew <= MO_32 : true;
>  }
>
> +static bool require_scale_zve64f(DisasContext *s)
> +{
> +    /* RVV + Zve64f = RVV. */
> +    if (has_ext(s, RVV)) {
> +        return true;
> +    }
> +
> +    /* Zve64f doesn't support FP64. (Section 18.2) */
> +    return s->ext_zve64f ? s->sew <= MO_16 : true;
> +}
> +
>  /* Destination vector register group cannot overlap source mask register. */
>  static bool require_vm(int vm, int vd)
>  {
> @@ -2331,7 +2342,8 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
>             require_scale_rvf(s) &&
>             (s->sew != MO_8) &&
>             vext_check_isa_ill(s) &&
> -           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
> +           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
> +           require_scale_zve64f(s);
>  }
>
>  /* OPFVV with WIDEN */
> @@ -2370,7 +2382,8 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
>             require_scale_rvf(s) &&
>             (s->sew != MO_8) &&
>             vext_check_isa_ill(s) &&
> -           vext_check_ds(s, a->rd, a->rs2, a->vm);
> +           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
> +           require_scale_zve64f(s);
>  }
>
>  /* OPFVF with WIDEN */
> @@ -2400,7 +2413,8 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
>             require_scale_rvf(s) &&
>             (s->sew != MO_8) &&
>             vext_check_isa_ill(s) &&
> -           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
> +           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
> +           require_scale_zve64f(s);
>  }
>
>  /* WIDEN OPFVV with WIDEN */
> @@ -2439,7 +2453,8 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
>             require_scale_rvf(s) &&
>             (s->sew != MO_8) &&
>             vext_check_isa_ill(s) &&
> -           vext_check_dd(s, a->rd, a->rs2, a->vm);
> +           vext_check_dd(s, a->rd, a->rs2, a->vm) &&
> +           require_scale_zve64f(s);
>  }
>
>  /* WIDEN OPFVF with WIDEN */
> @@ -2698,14 +2713,16 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
>  static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
>  {
>      return opfv_widen_check(s, a) &&
> -           require_rvf(s);
> +           require_rvf(s) &&
> +           require_zve64f(s);
>  }
>
>  static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
>  {
>      return opfv_widen_check(s, a) &&
>             require_scale_rvf(s) &&
> -           (s->sew != MO_8);
> +           (s->sew != MO_8) &&
> +           require_scale_zve64f(s);
>  }
>
>  #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
> @@ -2756,7 +2773,8 @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
>             require_scale_rvf(s) &&
>             vext_check_isa_ill(s) &&
>             /* OPFV widening instructions ignore vs1 check */
> -           vext_check_ds(s, a->rd, a->rs2, a->vm);
> +           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
> +           require_scale_zve64f(s);
>  }
>
>  #define GEN_OPFXV_WIDEN_TRANS(NAME)                                \
> --
> 2.31.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index d7e288b87f..9ca8d502b2 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -77,6 +77,17 @@  static bool require_zve64f(DisasContext *s)
     return s->ext_zve64f ? s->sew <= MO_32 : true;
 }
 
+static bool require_scale_zve64f(DisasContext *s)
+{
+    /* RVV + Zve64f = RVV. */
+    if (has_ext(s, RVV)) {
+        return true;
+    }
+
+    /* Zve64f doesn't support FP64. (Section 18.2) */
+    return s->ext_zve64f ? s->sew <= MO_16 : true;
+}
+
 /* Destination vector register group cannot overlap source mask register. */
 static bool require_vm(int vm, int vd)
 {
@@ -2331,7 +2342,8 @@  static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
+           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 /* OPFVV with WIDEN */
@@ -2370,7 +2382,8 @@  static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_ds(s, a->rd, a->rs2, a->vm);
+           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 /* OPFVF with WIDEN */
@@ -2400,7 +2413,8 @@  static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
+           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 /* WIDEN OPFVV with WIDEN */
@@ -2439,7 +2453,8 @@  static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_dd(s, a->rd, a->rs2, a->vm);
+           vext_check_dd(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 /* WIDEN OPFVF with WIDEN */
@@ -2698,14 +2713,16 @@  static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
 static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
-           require_rvf(s);
+           require_rvf(s) &&
+           require_zve64f(s);
 }
 
 static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           (s->sew != MO_8) &&
+           require_scale_zve64f(s);
 }
 
 #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -2756,7 +2773,8 @@  static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
            require_scale_rvf(s) &&
            vext_check_isa_ill(s) &&
            /* OPFV widening instructions ignore vs1 check */
-           vext_check_ds(s, a->rd, a->rs2, a->vm);
+           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 #define GEN_OPFXV_WIDEN_TRANS(NAME)                                \