Show patches with: Submitter = Alistair Francis       |    State = Action Required       |    Archived = No       |   1748 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,10/16] hw/riscv: allow ramfb on virt [PULL,01/16] target/riscv: fix vs() to return proper error code - - 2 - --- 2021-03-23 Alistair Francis New
[PULL,09/16] hw/riscv: Add fw_cfg support to virt [PULL,01/16] target/riscv: fix vs() to return proper error code - - 2 - --- 2021-03-23 Alistair Francis New
[PULL,08/16] target/riscv: Use background registers also for MSTATUS_MPV [PULL,01/16] target/riscv: fix vs() to return proper error code - - 1 - --- 2021-03-23 Alistair Francis New
[PULL,07/16] target/riscv: Make VSTIP and VSEIP read-only in hip [PULL,01/16] target/riscv: fix vs() to return proper error code - - 1 - --- 2021-03-23 Alistair Francis New
[PULL,06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions [PULL,01/16] target/riscv: fix vs() to return proper error code - - 1 - --- 2021-03-23 Alistair Francis New
[PULL,05/16] target/riscv: flush TLB pages if PMP permission has been changed [PULL,01/16] target/riscv: fix vs() to return proper error code - - 1 - --- 2021-03-23 Alistair Francis New
[PULL,04/16] target/riscv: add log of PMP permission checking [PULL,01/16] target/riscv: fix vs() to return proper error code - - 1 - --- 2021-03-23 Alistair Francis New
[PULL,03/16] target/riscv: propagate PMP permission to TLB page [PULL,01/16] target/riscv: fix vs() to return proper error code - - 1 - --- 2021-03-23 Alistair Francis New
[PULL,02/16] hw/char: disable ibex uart receive if the buffer is full [PULL,01/16] target/riscv: fix vs() to return proper error code - - 1 - --- 2021-03-23 Alistair Francis New
[PULL,01/16] target/riscv: fix vs() to return proper error code [PULL,01/16] target/riscv: fix vs() to return proper error code - - 2 - --- 2021-03-23 Alistair Francis New
[PULL,00/16] riscv-to-apply queue - - - - --- 2021-03-23 Alistair Francis New
[v1,5/5] target/riscv: Use RiscVException enum for CSR access RISC-V: Convert the CSR access functions to use - - - - --- 2021-03-17 Alistair Francis New
[v1,4/5] target/riscv: Use the RiscVException enum for CSR operations RISC-V: Convert the CSR access functions to use - - - - --- 2021-03-17 Alistair Francis New
[v1,3/5] target/riscv: Fix 32-bit HS mode access permissions RISC-V: Convert the CSR access functions to use - - - - --- 2021-03-17 Alistair Francis New
[v1,2/5] target/riscv: Use the RiscVException enum for CSR predicates RISC-V: Convert the CSR access functions to use - - - - --- 2021-03-17 Alistair Francis New
[v1,1/5] target/riscv: Convert the RISC-V exceptions to an enum RISC-V: Convert the CSR access functions to use - - 1 - --- 2021-03-17 Alistair Francis New
[PULL,v2,19/19] hw/riscv: virt: Map high mmio for PCIe [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,18/19] hw/riscv: virt: Limit RAM size in a 32-bit system [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,17/19] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,16/19] hw/riscv: Drop 'struct MemmapEntry' [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - - 2 - --- 2021-03-04 Alistair Francis New
[PULL,v2,15/19] MAINTAINERS: Add a SiFive machine section [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size 2 - 2 - --- 2021-03-04 Alistair Francis New
[PULL,v2,14/19] goldfish_rtc: re-arm the alarm after migration [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - - 2 - --- 2021-03-04 Alistair Francis New
[PULL,v2,13/19] docs/system: riscv: Add documentation for sifive_u machine [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - - 2 - --- 2021-03-04 Alistair Francis New
[PULL,v2,12/19] docs/system: Add RISC-V documentation [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,11/19] docs/system: Sort targets in alphabetical order [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,10/19] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,09/19] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,08/19] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,07/19] hw/ssi: Add SiFive SPI controller support [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,06/19] hw/block: m25p80: Add various ISSI flash information [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size 1 - - - --- 2021-03-04 Alistair Francis New
[PULL,v2,05/19] hw/block: m25p80: Add ISSI SPI flash support [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size 1 - - - --- 2021-03-04 Alistair Francis New
[PULL,v2,04/19] target-riscv: support QMP dump-guest-memory [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - - 3 - --- 2021-03-04 Alistair Francis New
[PULL,v2,03/19] roms/opensbi: Upgrade from v0.8 to v0.9 [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-03-04 Alistair Francis New
[PULL,v2,02/19] hw/misc: sifive_u_otp: Use error_report() when block operation fails [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - - 2 - --- 2021-03-04 Alistair Francis New
[PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size [PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size - - 2 - --- 2021-03-04 Alistair Francis New
[PULL,v2,00/19] riscv-to-apply queue - - - - --- 2021-03-04 Alistair Francis New
[PULL,19/19] hw/riscv: virt: Map high mmio for PCIe [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-02-18 Alistair Francis New
[PULL,18/19] hw/riscv: virt: Limit RAM size in a 32-bit system [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-02-18 Alistair Francis New
[PULL,17/19] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-02-18 Alistair Francis New
[PULL,16/19] hw/riscv: Drop 'struct MemmapEntry' [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 2 - --- 2021-02-18 Alistair Francis New
[PULL,15/19] MAINTAINERS: Add a SiFive machine section [PULL,01/19] target/riscv: Declare csr_ops[] with a known size 2 - 2 - --- 2021-02-18 Alistair Francis New
[PULL,14/19] goldfish_rtc: re-arm the alarm after migration [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 2 - --- 2021-02-18 Alistair Francis New
[PULL,13/19] docs/system: riscv: Add documentation for sifive_u machine [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 2 - --- 2021-02-18 Alistair Francis New
[PULL,12/19] docs/system: Add RISC-V documentation [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-02-18 Alistair Francis New
[PULL,11/19] docs/system: Sort targets in alphabetical order [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-02-18 Alistair Francis New
[PULL,10/19] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-02-18 Alistair Francis New
[PULL,09/19] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-02-18 Alistair Francis New
[PULL,08/19] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-02-18 Alistair Francis New
[PULL,07/19] hw/ssi: Add SiFive SPI controller support [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-02-18 Alistair Francis New
[PULL,06/19] hw/block: m25p80: Add various ISSI flash information [PULL,01/19] target/riscv: Declare csr_ops[] with a known size 1 - - - --- 2021-02-18 Alistair Francis New
[PULL,05/19] hw/block: m25p80: Add ISSI SPI flash support [PULL,01/19] target/riscv: Declare csr_ops[] with a known size 1 - - - --- 2021-02-18 Alistair Francis New
[PULL,04/19] target-riscv: support QMP dump-guest-memory [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 3 - --- 2021-02-18 Alistair Francis New
[PULL,03/19] roms/opensbi: Upgrade from v0.8 to v0.9 [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 1 - --- 2021-02-18 Alistair Francis New
[PULL,02/19] hw/misc: sifive_u_otp: Use error_report() when block operation fails [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 2 - --- 2021-02-18 Alistair Francis New
[PULL,01/19] target/riscv: Declare csr_ops[] with a known size [PULL,01/19] target/riscv: Declare csr_ops[] with a known size - - 2 - --- 2021-02-18 Alistair Francis New
[PULL,00/19] riscv-to-apply queue - - - - --- 2021-02-18 Alistair Francis New
[v1,1/1] MAINTAINERS: Add a SiFIve machine section [v1,1/1] MAINTAINERS: Add a SiFIve machine section 2 - 2 - --- 2021-02-09 Alistair Francis New
[v2,1/1] linux-user/signal: Decode waitid si_code [v2,1/1] linux-user/signal: Decode waitid si_code - - 1 1 --- 2021-01-19 Alistair Francis New
[PULL,12/12] riscv: Pass RISCVHartArrayState by pointer [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 3 2 - --- 2021-01-17 Alistair Francis New
[PULL,11/12] target/riscv: Remove built-in GDB XML files for CSRs [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - - 1 - --- 2021-01-17 Alistair Francis New
[PULL,10/12] target/riscv: Generate the GDB XML file for CSR registers dynamically [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - - 1 - --- 2021-01-17 Alistair Francis New
[PULL,09/12] target/riscv: Add CSR name in the CSR function table [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - - 1 - --- 2021-01-17 Alistair Francis New
[PULL,08/12] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - - 1 - --- 2021-01-17 Alistair Francis New
[PULL,07/12] hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 3 1 - --- 2021-01-17 Alistair Francis New
[PULL,06/12] hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - - 2 - --- 2021-01-17 Alistair Francis New
[PULL,05/12] target/riscv/pmp: Raise exception if no PMP entry is configured [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - - 1 - --- 2021-01-17 Alistair Francis New
[PULL,04/12] RISC-V: Place DTB at 3GB boundary instead of 4GB [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 1 1 1 --- 2021-01-17 Alistair Francis New
[PULL,03/12] gdb: riscv: Add target description [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - - 3 - --- 2021-01-17 Alistair Francis New
[PULL,02/12] hw/block: m25p80: Implement AAI-WP command support for SST flashes [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - - 1 - --- 2021-01-17 Alistair Francis New
[PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled [PULL,01/12] hw/block: m25p80: Don't write to flash if write is disabled - 1 2 - --- 2021-01-17 Alistair Francis New
[PULL,00/12] riscv-to-apply queue - - - - --- 2021-01-17 Alistair Francis New
[v1,1/1] riscv: Pass RISCVHartArrayState by pointer [v1,1/1] riscv: Pass RISCVHartArrayState by pointer - 3 2 - --- 2021-01-15 Alistair Francis New
[v1,1/1] linux-user/signal: Decode waitid si_code [v1,1/1] linux-user/signal: Decode waitid si_code - - - 1 --- 2020-12-19 Alistair Francis New
[PULL,23/23] riscv/opentitan: Update the OpenTitan memory layout [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - - - --- 2020-12-18 Alistair Francis New
[PULL,22/23] hw/riscv: Use the CPU to determine if 32-bit [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - 1 - --- 2020-12-18 Alistair Francis New
[PULL,21/23] target/riscv: cpu: Set XLEN independently from target [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 1 --- 2020-12-18 Alistair Francis New
[PULL,20/23] target/riscv: csr: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 1 --- 2020-12-18 Alistair Francis New
[PULL,19/23] target/riscv: cpu_helper: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 3 1 --- 2020-12-18 Alistair Francis New
[PULL,18/23] target/riscv: cpu: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 3 1 --- 2020-12-18 Alistair Francis New
[PULL,17/23] target/riscv: Specify the XLEN for CPUs [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 3 1 --- 2020-12-18 Alistair Francis New
[PULL,16/23] target/riscv: Add a riscv_cpu_is_32bit() helper function [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 1 --- 2020-12-18 Alistair Francis New
[PULL,15/23] target/riscv: fpu_helper: Match function defs in HELPER macros [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - - - --- 2020-12-18 Alistair Francis New
[PULL,14/23] hw/riscv: sifive_u: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 1 --- 2020-12-18 Alistair Francis New
[PULL,13/23] hw/riscv: spike: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 - --- 2020-12-18 Alistair Francis New
[PULL,12/23] hw/riscv: virt: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 1 --- 2020-12-18 Alistair Francis New
[PULL,11/23] hw/riscv: boot: Remove compile time XLEN checks [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 1 --- 2020-12-18 Alistair Francis New
[PULL,10/23] riscv: virt: Remove target macro conditionals [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 1 --- 2020-12-18 Alistair Francis New
[PULL,09/23] riscv: spike: Remove target macro conditionals [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 - --- 2020-12-18 Alistair Francis New
[PULL,08/23] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 2 1 --- 2020-12-18 Alistair Francis New
[PULL,07/23] hw/riscv: Expand the is 32-bit check to support more CPUs [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 1 - --- 2020-12-18 Alistair Francis New
[PULL,06/23] intc/ibex_plic: Clear interrupts that occur during claim process [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - - 1 --- 2020-12-18 Alistair Francis New
[PULL,05/23] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - 1 - --- 2020-12-18 Alistair Francis New
[PULL,04/23] target/riscv: Fix the bug of HLVX/HLV/HSV [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - 1 - --- 2020-12-18 Alistair Francis New
[PULL,03/23] hw/core/register.c: Don't use '#' flag of printf format [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - 1 - --- 2020-12-18 Alistair Francis New
[PULL,02/23] hw/riscv: microchip_pfsoc: add QSPI NOR flash [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB 1 - 1 - --- 2020-12-18 Alistair Francis New
[PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB [PULL,01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB - - 1 - --- 2020-12-18 Alistair Francis New
[PULL,00/23] riscv-to-apply queue - - - - --- 2020-12-18 Alistair Francis New
[v4,16/16] hw/riscv: Use the CPU to determine if 32-bit RISC-V: Start to remove xlen preprocess - - 1 - --- 2020-12-16 Alistair Francis New
[v4,15/16] target/riscv: cpu: Set XLEN independently from target RISC-V: Start to remove xlen preprocess 1 - 2 1 --- 2020-12-16 Alistair Francis New
[v4,14/16] target/riscv: csr: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess 1 - 2 1 --- 2020-12-16 Alistair Francis New
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